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@ -15,7 +15,7 @@ |
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#ifndef CONFIG_SL351x_RXTOE
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//#define CONFIG_SL351x_RXTOE 1
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@@ -126,7 +130,6 @@
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@@ -126,7 +130,6 @@ static char _debug_prefetch_buf[_DEBUG_P
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*************************************************************/
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static int gmac_initialized = 0;
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TOE_INFO_T toe_private_data;
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@ -23,7 +23,7 @@ |
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static int rx_poll_enabled;
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spinlock_t gmac_fq_lock;
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unsigned int FLAG_SWITCH;
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@@ -190,7 +193,7 @@
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@@ -190,7 +193,7 @@ void mac_get_sw_tx_weight(struct net_dev
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void mac_set_sw_tx_weight(struct net_device *dev, char *weight);
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void mac_get_hw_tx_weight(struct net_device *dev, char *weight);
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void mac_set_hw_tx_weight(struct net_device *dev, char *weight);
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@ -32,7 +32,7 @@ |
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#ifdef VITESSE_G5SWITCH
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extern int Get_Set_port_status(void);
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@@ -295,12 +298,14 @@
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@@ -295,12 +298,14 @@ static int __init gmac_init_module(void)
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for(j = 0; i<CONFIG_MAC_NUM; j++)
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{
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i=j;
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@ -47,7 +47,7 @@ |
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tp = (GMAC_INFO_T *)&toe_private_data.gmac[i];
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tp->dev = NULL;
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@@ -459,7 +464,7 @@
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@@ -459,7 +464,7 @@ void mac_init_drv(void)
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toe->gmac[1].dma_base_addr = TOE_GMAC1_DMA_BASE;
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toe->gmac[0].auto_nego_cfg = 1;
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toe->gmac[1].auto_nego_cfg = 1;
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@ -56,7 +56,7 @@ |
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toe->gmac[0].speed_cfg = GMAC_SPEED_1000;
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toe->gmac[1].speed_cfg = GMAC_SPEED_1000;
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#else
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@@ -508,7 +513,7 @@
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@@ -508,7 +513,7 @@ void mac_init_drv(void)
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// Write GLOBAL_QUEUE_THRESHOLD_REG
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threshold.bits32 = 0;
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threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
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@ -65,7 +65,7 @@ |
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threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256/4 :
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TOE_HW_FREEQ_DESC_NUM/4;
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threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256/4 :
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@@ -613,18 +618,25 @@
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@@ -613,18 +618,25 @@ static void toe_init_free_queue(void)
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rwptr_reg.bits.rptr = 0;
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toe->fq_rx_rwptr.bits32 = rwptr_reg.bits32;
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writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
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@ -93,7 +93,7 @@ |
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// toe->rx_skb[i] = skb;
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sw_desc_ptr->word2.buf_adr = (unsigned int)__pa(skb->data);
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// consistent_sync((unsigned int)desc_ptr, sizeof(GMAC_RXDESC_T), PCI_DMA_TODEVICE);
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@@ -851,14 +863,14 @@
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@@ -851,14 +863,14 @@ static void toe_init_hwtx_queue(void)
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*----------------------------------------------------------------------*/
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static void toe_init_default_queue(void)
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{
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@ -112,7 +112,7 @@ |
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if (!desc_ptr)
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{
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printk("%s::DMA_MALLOC fail !\n",__func__);
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@@ -866,14 +878,17 @@
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@@ -866,14 +878,17 @@ static void toe_init_default_queue(void)
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}
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memset((void *)desc_ptr, 0, TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T));
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toe->gmac[0].default_desc_base = (unsigned int)desc_ptr;
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@ -131,7 +131,7 @@ |
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if (!desc_ptr)
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{
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printk("%s::DMA_MALLOC fail !\n",__func__);
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@@ -1071,12 +1086,16 @@
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@@ -1071,12 +1086,16 @@ static void toe_init_gmac(struct net_dev
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data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) & ~tp->intr0_selected;
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writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
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@ -148,7 +148,7 @@ |
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data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG) & ~tp->intr4_selected;
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writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
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}
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@@ -1176,11 +1195,11 @@
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@@ -1176,11 +1195,11 @@ static int toe_gmac_init_chip(struct net
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GMAC_CONFIG2_T config2_val;
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GMAC_CONFIG0_T config0,config0_mask;
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GMAC_CONFIG1_T config1;
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@ -162,7 +162,7 @@ |
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// GMAC_HASH_ENABLE_REG0_T hash_ctrl;
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//
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#if 0 /* mac address will be set in late_initcall */
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@@ -1202,24 +1221,23 @@
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@@ -1202,24 +1221,23 @@ static int toe_gmac_init_chip(struct net
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// config1.bits32 = 0x002004; //next version
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/* set flow control threshold */
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config1.bits32 = 0;
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@ -195,7 +195,7 @@ |
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// gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL0,0x0,0xffffffff);
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// gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL1,0x0,0xffffffff);
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@@ -1249,7 +1267,7 @@
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@@ -1249,7 +1267,7 @@ static int toe_gmac_init_chip(struct net
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config0.bits.dis_rx = 1; /* disable rx */
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config0.bits.dis_tx = 1; /* disable tx */
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config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
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@ -204,7 +204,7 @@ |
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config0.bits.rgmii_en = 0;
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config0.bits.rgmm_edge = 1;
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config0.bits.rxc_inv = 0;
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@@ -1342,6 +1360,9 @@
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@@ -1342,6 +1360,9 @@ static int toe_gmac_init_chip(struct net
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gmac_write_reg(tp->dma_base_addr, GMAC_AHB_WEIGHT_REG, ahb_weight.bits32, ahb_weight_mask.bits32);
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#endif
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@ -214,7 +214,7 @@ |
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#if defined(CONFIG_SL351x_NAT) || defined(CONFIG_SL351x_RXTOE)
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gmac_write_reg(tp->dma_base_addr, GMAC_SPR0, IPPROTO_TCP, 0xffffffff);
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#endif
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@@ -1552,7 +1573,7 @@
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@@ -1552,7 +1573,7 @@ static void toe_gmac_tx_complete(GMAC_I
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rwptr.bits32 = readl(swtxq->rwptr_reg);
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if (rwptr.bits.rptr == swtxq->finished_idx)
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break;
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@ -223,7 +223,7 @@ |
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// consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_FROMDEVICE);
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word0.bits32 = curr_desc->word0.bits32;
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word1.bits32 = curr_desc->word1.bits32;
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@@ -1573,6 +1594,7 @@
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@@ -1573,6 +1594,7 @@ static void toe_gmac_tx_complete(GMAC_I
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swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
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curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
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word0.bits32 = curr_desc->word0.bits32;
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@ -231,7 +231,7 @@ |
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#ifdef _DUMP_TX_TCP_CONTENT
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if (curr_desc->word0.bits.buffer_size < 16)
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{
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@@ -1592,12 +1614,12 @@
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@@ -1592,12 +1614,12 @@ static void toe_gmac_tx_complete(GMAC_I
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word0.bits.status_tx_ok = 0;
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if (swtxq->tx_skb[swtxq->finished_idx])
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{
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@ -248,7 +248,7 @@ |
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curr_desc->word0.bits32 = word0.bits32;
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swtxq->curr_finished_desc = (GMAC_TXDESC_T *)curr_desc;
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swtxq->total_finished++;
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@@ -1624,31 +1646,29 @@
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@@ -1624,31 +1646,29 @@ static void toe_gmac_tx_complete(GMAC_I
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*----------------------------------------------------------------------*/
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static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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@ -294,7 +294,7 @@ |
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total_pages = snd_pages;
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#endif
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@@ -1664,13 +1684,6 @@
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@@ -1664,13 +1684,6 @@ static int gmac_start_xmit(struct sk_buf
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}
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#endif
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@ -308,7 +308,7 @@ |
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#ifdef GMAC_USE_TXQ0
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#define tx_qid 0
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#endif
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@@ -1703,9 +1716,9 @@
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@@ -1703,9 +1716,9 @@ static int gmac_start_xmit(struct sk_buf
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toe_gmac_tx_complete(tp, tx_qid, dev, 0);
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if (wptr >= swtxq->finished_idx)
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@ -320,7 +320,7 @@ |
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if (free_desc < snd_pages)
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{
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// spin_unlock(&tp->tx_mutex);
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@@ -2063,9 +2076,10 @@
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@@ -2063,9 +2076,10 @@ void mac_start_txdma(struct net_device *
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struct net_device_stats * gmac_get_stats(struct net_device *dev)
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{
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GMAC_INFO_T *tp = (GMAC_INFO_T *)dev->priv;
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@ -333,7 +333,7 @@ |
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if (netif_running(dev))
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{
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@@ -2073,10 +2087,14 @@
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@@ -2073,10 +2087,14 @@ struct net_device_stats * gmac_get_stats
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// spin_lock_irqsave(&tp->lock,flags);
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pkt_drop = gmac_read_reg(tp->base_addr,GMAC_IN_DISCARDS);
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pkt_error = gmac_read_reg(tp->base_addr,GMAC_IN_ERRORS);
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@ -348,7 +348,7 @@ |
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return &tp->ifStatics;
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}
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@@ -2401,36 +2419,63 @@
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@@ -2401,36 +2419,63 @@ static int gmac_close(struct net_device
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* toe_gmac_fill_free_q
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* allocate buffers for free queue.
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*----------------------------------------------------------------------*/
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@ -425,7 +425,7 @@ |
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}
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// EXPORT_SYMBOL(toe_gmac_fill_free_q);
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@@ -2442,14 +2487,14 @@
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@@ -2442,14 +2487,14 @@ static void gmac_registers(const char *m
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unsigned int status3;
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unsigned int status4;
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@ -442,7 +442,7 @@ |
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printk("status: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
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status0, status1, status2, status3, status4);
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@@ -2468,8 +2513,9 @@
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@@ -2468,8 +2513,9 @@ static void gmac_registers(const char *m
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status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
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status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
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@ -454,7 +454,7 @@ |
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}
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/*----------------------------------------------------------------------
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* toe_gmac_interrupt
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@@ -2485,75 +2531,44 @@
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@@ -2485,75 +2531,44 @@ static irqreturn_t toe_gmac_interrupt (i
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unsigned int status3;
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unsigned int status4;
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@ -549,7 +549,7 @@ |
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{
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#define G1_INTR0_BITS (GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
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#define G0_INTR0_BITS (GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
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@@ -2563,7 +2578,7 @@
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@@ -2563,7 +2578,7 @@ if (1)
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// because they should pass packets to upper layer
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if (tp->port_id == 0)
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{
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@ -558,7 +558,7 @@ |
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{
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if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
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tp->hwtxq[3].eof_cnt++;
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@@ -2574,50 +2589,51 @@
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@@ -2574,50 +2589,51 @@ if (1)
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if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
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tp->hwtxq[0].eof_cnt++;
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}
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@ -646,7 +646,7 @@ |
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{
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if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
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tp->hwtxq[3].eof_cnt++;
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@@ -2629,14 +2645,14 @@
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@@ -2629,14 +2645,14 @@ if (1)
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tp->hwtxq[0].eof_cnt++;
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}
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@ -665,7 +665,7 @@ |
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BUG_ON(rx_poll_enabled == 1);
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@@ -2646,7 +2662,7 @@
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@@ -2646,7 +2662,7 @@ if (1)
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data32 &= ~(DEFAULT_Q1_INT_BIT);
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writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
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@ -674,7 +674,7 @@ |
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data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
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data32 &= ~DEFAULT_Q1_INT_BIT;
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writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
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@@ -2656,24 +2672,21 @@
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@@ -2656,24 +2672,21 @@ if (1)
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writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
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#endif
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@ -706,7 +706,7 @@ |
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}
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// Interrupt Status 0
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@@ -2814,676 +2827,93 @@
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@@ -2814,676 +2827,93 @@ if (1)
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}
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}
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@ -1457,7 +1457,7 @@ |
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{
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case GMAC_PHY_GMII:
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mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
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@@ -3552,6 +2982,7 @@
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@@ -3552,6 +2982,7 @@ void gmac_set_phy_status(struct net_devi
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status.bits.link = LINK_DOWN;
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// clear_bit(__LINK_STATE_START, &dev->state);
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printk("Link Down (0x%04x) ", reg_val);
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@ -1465,7 +1465,7 @@ |
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if(Giga_switch == 1)
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{
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wan_port_id = 1;
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@@ -3565,6 +2996,7 @@
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@@ -3565,6 +2996,7 @@ void gmac_set_phy_status(struct net_devi
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storlink_ctl.link[ tp->port_id] = 0;
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#endif
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}
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@ -1473,7 +1473,7 @@ |
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}
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else
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{
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@@ -3572,6 +3004,7 @@
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@@ -3572,6 +3004,7 @@ void gmac_set_phy_status(struct net_devi
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status.bits.link = LINK_UP;
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// set_bit(__LINK_STATE_START, &dev->state);
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printk("Link Up (0x%04x) ",reg_val);
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@ -1481,7 +1481,7 @@ |
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if(Giga_switch == 1)
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{
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wan_port_id = 1;
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@@ -3585,6 +3018,7 @@
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@@ -3585,6 +3018,7 @@ void gmac_set_phy_status(struct net_devi
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storlink_ctl.link[ tp->port_id] = 1;
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#endif
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}
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@ -1489,7 +1489,7 @@ |
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}
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// value = mii_read(PHY_ADDR,0x05);
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@@ -3863,6 +3297,7 @@
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@@ -3863,6 +3297,7 @@ void gmac_get_phy_status(struct net_devi
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}
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}
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status.bits.link = LINK_UP; /* link up */
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@ -1497,7 +1497,7 @@ |
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if(Giga_switch==1)
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{
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wan_port_id = 1;
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@@ -3874,6 +3309,7 @@
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@@ -3874,6 +3309,7 @@ void gmac_get_phy_status(struct net_devi
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storlink_ctl.link[ tp->port_id] = 1;
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#endif
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}
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@ -1505,7 +1505,7 @@ |
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if ((ability & 0x20)==0x20)
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{
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if (tp->flow_control_enable == 0)
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@@ -3914,6 +3350,7 @@
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@@ -3914,6 +3350,7 @@ void gmac_get_phy_status(struct net_devi
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else
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{
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status.bits.link = LINK_DOWN; /* link down */
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@ -1513,7 +1513,7 @@ |
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if(Giga_switch == 1)
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{
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wan_port_id = 1;
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@@ -3925,6 +3362,7 @@
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@@ -3925,6 +3362,7 @@ void gmac_get_phy_status(struct net_devi
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storlink_ctl.link[ tp->port_id] = 0;
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#endif
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}
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@ -1521,7 +1521,7 @@ |
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if (tp->pre_phy_status == LINK_UP)
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{
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printk("GMAC-%d LINK_Down......\n",tp->port_id);
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@@ -4298,86 +3736,102 @@
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@@ -4298,86 +3736,102 @@ static void gmac_set_rx_mode(struct net_
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}
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#ifdef CONFIG_SL_NAPI
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@ -1685,7 +1685,7 @@ |
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{
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good_frame = 0;
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if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
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@@ -4388,7 +3842,6 @@
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@@ -4388,7 +3842,6 @@ static int gmac_rx_poll(struct net_devic
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{
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if (rx_status == 4 || rx_status == 7)
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isPtr->rx_crc_errors++;
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@ -1693,7 +1693,7 @@ |
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}
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#ifdef SL351x_GMAC_WORKAROUND
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else if (pkt_size < 60)
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@@ -4407,17 +3860,32 @@
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@@ -4407,17 +3860,32 @@ static int gmac_rx_poll(struct net_devic
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}
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}
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#endif
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@ -1731,7 +1731,7 @@ |
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|
#ifdef SL351x_GMAC_WORKAROUND
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|
if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
|
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|
@@ -4432,225 +3900,118 @@
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|
@@ -4432,225 +3900,118 @@ static int gmac_rx_poll(struct net_devic
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|
}
|
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|
|
tp->short_frames_cnt = 0;
|
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|
#endif
|
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|
@ -2015,7 +2015,7 @@ |
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|
}
|
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|
#endif
|
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|
@@ -5114,6 +4475,7 @@
|
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|
@@ -5114,6 +4475,7 @@ void sl351x_poll_gmac_hanged_status(u32
|
|
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|
|
{
|
|
|
|
|
sl351x_nat_workaround_cnt++;
|
|
|
|
|
sl351x_nat_workaround_handler();
|
|
|
|
|
@ -2023,7 +2023,7 @@ |
|
|
|
|
}
|
|
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|
|
#endif
|
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|
|
#endif
|
|
|
|
|
@@ -5124,6 +4486,7 @@
|
|
|
|
|
@@ -5124,6 +4486,7 @@ void sl351x_poll_gmac_hanged_status(u32
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
do_workaround:
|
|
|
|
|
@ -2031,7 +2031,7 @@ |
|
|
|
|
|
|
|
|
|
gmac_initialized = 0;
|
|
|
|
|
if (hanged_state)
|
|
|
|
|
@@ -5290,6 +4653,7 @@
|
|
|
|
|
@@ -5290,6 +4653,7 @@ static void sl351x_gmac_release_swtx_q(v
|
|
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|
|
GMAC_SWTXQ_T *swtxq;
|
|
|
|
|
DMA_RWPTR_T rwptr;
|
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|
|
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|
|
@ -2039,7 +2039,7 @@ |
|
|
|
|
toe = (TOE_INFO_T *)&toe_private_data;
|
|
|
|
|
tp = (GMAC_INFO_T *)&toe->gmac[0];
|
|
|
|
|
for (i=0; i<GMAC_NUM; i++, tp++)
|
|
|
|
|
@@ -5341,6 +4705,7 @@
|
|
|
|
|
@@ -5341,6 +4705,7 @@ static void sl351x_gmac_release_rx_q(voi
|
|
|
|
|
volatile GMAC_RXDESC_T *curr_desc;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
|
|
|
|
|
@ -2047,7 +2047,7 @@ |
|
|
|
|
toe = (TOE_INFO_T *)&toe_private_data;
|
|
|
|
|
tp = (GMAC_INFO_T *)&toe->gmac[0];
|
|
|
|
|
for (i=0; i<GMAC_NUM; i++, tp++)
|
|
|
|
|
@@ -5374,6 +4739,7 @@
|
|
|
|
|
@@ -5374,6 +4739,7 @@ static void sl351x_gmac_release_class_q(
|
|
|
|
|
volatile GMAC_RXDESC_T *curr_desc;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
|
|
|
|
|
@ -2055,7 +2055,7 @@ |
|
|
|
|
toe = (TOE_INFO_T *)&toe_private_data;
|
|
|
|
|
classq = (CLASSQ_INFO_T *)&toe->classq[0];
|
|
|
|
|
for (i=0; i<TOE_CLASS_QUEUE_NUM; i++, classq++)
|
|
|
|
|
@@ -5410,6 +4776,7 @@
|
|
|
|
|
@@ -5410,6 +4776,7 @@ static void sl351x_gmac_release_toe_q(vo
|
|
|
|
|
GMAC_RXDESC_T *toe_curr_desc;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
|
|
|
|
|
|
Gabor Juhos
16 years ago