Signed-off-by: Tim Harvey <tharvey@gateworks.com> target/linux/cns3xxx/patches-3.3/470-gpio_irq.patch | 536 ++++++++++++++++++++ 1 file changed, 536 insertions(+) SVN-Revision: 33648master
parent
bca070dfbe
commit
6b778f57aa
@ -0,0 +1,536 @@ |
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--- a/arch/arm/mach-cns3xxx/Makefile
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+++ b/arch/arm/mach-cns3xxx/Makefile
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@@ -1,4 +1,4 @@
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-obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
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+obj-$(CONFIG_ARCH_CNS3XXX) += core.o gpio.o pm.o devices.o
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obj-$(CONFIG_PCI) += pcie.o
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obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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obj-$(CONFIG_MACH_GW2388) += laguna.o
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -199,7 +199,10 @@ static void __init cns3420_init(void)
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cns3xxx_ahci_init();
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cns3xxx_sdhci_init();
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-
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+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
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+ NR_IRQS_CNS3XXX);
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+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
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+ NR_IRQS_CNS3XXX + 32);
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cns3xxx_pcie_init(0x3);
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pm_power_off = cns3xxx_power_off;
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--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -21,7 +21,6 @@
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#include <asm/hardware/gic.h>
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#include <asm/smp_twd.h>
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#include <asm/hardware/cache-l2x0.h>
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-#include <asm/gpio.h>
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#include <mach/cns3xxx.h>
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#include "core.h"
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@@ -83,73 +82,12 @@ static struct map_desc cns3xxx_io_desc[]
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},
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};
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-static inline void gpio_line_config(u8 line, u32 direction)
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-{
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- u32 reg;
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- if (direction) {
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- if (line < 32) {
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- reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- reg |= (1 << line);
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- __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- } else {
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- reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- reg |= (1 << (line - 32));
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- __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- }
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- } else {
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- if (line < 32) {
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- reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- reg &= ~(1 << line);
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- __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- } else {
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- reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- reg &= ~(1 << (line - 32));
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- __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- }
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- }
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-}
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-
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-static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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-{
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- gpio_line_config(gpio, CNS3XXX_GPIO_IN);
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- return 0;
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-}
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-
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-static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
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-{
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- gpio_line_set(gpio, level);
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- gpio_line_config(gpio, CNS3XXX_GPIO_OUT);
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- return 0;
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-}
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-
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-static int cns3xxx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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-{
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- return gpio_get_value(gpio);
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-}
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-
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-static void cns3xxx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
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-{
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- gpio_set_value(gpio, value);
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-}
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-
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-static struct gpio_chip cns3xxx_gpio_chip = {
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- .label = "CNS3XXX_GPIO_CHIP",
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- .direction_input = cns3xxx_gpio_direction_input,
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- .direction_output = cns3xxx_gpio_direction_output,
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- .get = cns3xxx_gpio_get_value,
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- .set = cns3xxx_gpio_set_value,
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- .base = 0,
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- .ngpio = 64,
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-};
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-
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void __init cns3xxx_common_init(void)
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{
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
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#endif
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iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
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-
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- gpiochip_add(&cns3xxx_gpio_chip);
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}
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/* used by entry-macro.S */
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--- /dev/null
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+++ b/arch/arm/mach-cns3xxx/gpio.c
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@@ -0,0 +1,277 @@
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+/*
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+ * Copyright 2012 Gateworks Corporation
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+ * Chris Lang <clang@gateworks.com>
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+ * Tim Harvey <tharvey@gateworks.com>
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+ *
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+ * This file is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License, Version 2, as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/init.h>
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/gpio.h>
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+#include <linux/irq.h>
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+
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+#include <asm/mach/irq.h>
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+
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+/*
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+ * Registers
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+ */
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+#define GPIO_INPUT 0x04
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+#define GPIO_DIR 0x08
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+#define GPIO_SET 0x10
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+#define GPIO_CLEAR 0x14
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+#define GPIO_INTERRUPT_ENABLE 0x20
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+#define GPIO_INTERRUPT_RAW_STATUS 0x24
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+#define GPIO_INTERRUPT_MASKED_STATUS 0x28
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+#define GPIO_INTERRUPT_MASK 0x2C
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+#define GPIO_INTERRUPT_CLEAR 0x30
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+#define GPIO_INTERRUPT_TRIGGER_METHOD 0x34
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+#define GPIO_INTERRUPT_TRIGGER_BOTH_EDGES 0x38
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+#define GPIO_INTERRUPT_TRIGGER_TYPE 0x3C
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+
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+#define GPIO_INTERRUPT_TRIGGER_METHOD_EDGE 0
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+#define GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL 1
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+#define GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE 0
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+#define GPIO_INTERRUPT_TRIGGER_EDGE_BOTH 1
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+#define GPIO_INTERRUPT_TRIGGER_TYPE_RISING 0
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+#define GPIO_INTERRUPT_TRIGGER_TYPE_FALLING 1
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+#define GPIO_INTERRUPT_TRIGGER_TYPE_HIGH 0
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+#define GPIO_INTERRUPT_TRIGGER_TYPE_LOW 1
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+
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+struct cns3xxx_gpio_chip {
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+ struct gpio_chip chip;
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+ spinlock_t lock;
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+ void __iomem *base;
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+ int secondary_irq_base;
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+};
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+
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+static struct cns3xxx_gpio_chip cns3xxx_gpio_chips[2];
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+static int cns3xxx_gpio_chip_count;
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+
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+static inline void
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+__set_direction(struct cns3xxx_gpio_chip *cchip, unsigned pin, int input)
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+{
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+ u32 reg;
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+
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+ reg = __raw_readl(cchip->base + GPIO_DIR);
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+ if (input)
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+ reg |= 1 << pin;
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+ else
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+ reg &= !(1 << pin);
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+ __raw_writel(reg, cchip->base + GPIO_DIR);
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+}
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+
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+/*
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+ * GENERIC_GPIO primatives
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+ */
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+static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
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+{
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+ struct cns3xxx_gpio_chip *cchip =
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+ container_of(chip, struct cns3xxx_gpio_chip, chip);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&cchip->lock, flags);
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+ __set_direction(cchip, pin, 1);
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+ spin_unlock_irqrestore(&cchip->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int cns3xxx_gpio_get(struct gpio_chip *chip, unsigned pin)
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+{
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+ struct cns3xxx_gpio_chip *cchip =
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+ container_of(chip, struct cns3xxx_gpio_chip, chip);
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+ int val;
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+
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+ val = ((__raw_readl(cchip->base + GPIO_INPUT) >> pin) & 0x1);
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+
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+ return val;
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+}
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+
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+static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int level)
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+{
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+ struct cns3xxx_gpio_chip *cchip =
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+ container_of(chip, struct cns3xxx_gpio_chip, chip);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&cchip->lock, flags);
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+ if (level)
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+ __raw_writel(1 << pin, cchip->base + GPIO_SET);
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+ else
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+ __raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
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+ __set_direction(cchip, pin, 0);
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+ spin_unlock_irqrestore(&cchip->lock, flags);
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+
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+ return 0;
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+}
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+
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+static void cns3xxx_gpio_set(struct gpio_chip *chip, unsigned pin,
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+ int level)
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+{
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+ struct cns3xxx_gpio_chip *cchip =
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+ container_of(chip, struct cns3xxx_gpio_chip, chip);
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+
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+ if (level)
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+ __raw_writel(1 << pin, cchip->base + GPIO_SET);
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+ else
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+ __raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
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+}
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+
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+static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
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+{
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+ struct cns3xxx_gpio_chip *cchip =
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+ container_of(chip, struct cns3xxx_gpio_chip, chip);
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+
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+ return cchip->secondary_irq_base + pin;
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+}
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+
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+
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+/*
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+ * IRQ support
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+ */
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+
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+/* one interrupt per GPIO controller (GPIOA/GPIOB)
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+ * this is called in task context, with IRQs enabled
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+ */
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+static void cns3xxx_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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+{
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+ struct cns3xxx_gpio_chip *cchip = irq_get_handler_data(irq);
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+ struct irq_chip *chip = irq_get_chip(irq);
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+ struct irq_chip_generic *gc = irq_desc_get_chip_data(desc);
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+ struct irq_chip_type *ct = gc->chip_types;
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+ u16 i;
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+ u32 reg;
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+
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+ chained_irq_enter(chip, desc); /* mask and ack the base interrupt */
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+
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+ /* see which pin(s) triggered the interrupt */
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+ reg = __raw_readl(cchip->base + GPIO_INTERRUPT_RAW_STATUS);
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+ for (i = 0; i < 32; i++) {
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+ if (reg & (1 << i)) {
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+ /* let the generic IRQ layer handle an interrupt */
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+ generic_handle_irq(cchip->secondary_irq_base + i);
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+ }
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+ }
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+
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+ chained_irq_exit(chip, desc); /* unmask the base interrupt */
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+}
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+
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+static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype)
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+{
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+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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+ struct cns3xxx_gpio_chip *cchip = gc->private;
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+ u32 gpio = d->irq - cchip->secondary_irq_base;
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+ unsigned long flags;
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+ u32 method, edges, type;
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+
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+ spin_lock_irqsave(&cchip->lock, flags);
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+ method = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
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+ edges = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
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+ type = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
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+ method &= ~(1 << gpio);
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+ edges &= ~(1 << gpio);
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+ type &= ~(1 << gpio);
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+
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+ switch(irqtype) {
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+ case IRQ_TYPE_EDGE_RISING:
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+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
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+ edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
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+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_RISING << gpio);
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+ break;
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+ case IRQ_TYPE_EDGE_FALLING:
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+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
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+ edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
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+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_FALLING << gpio);
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+ break;
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+ case IRQ_TYPE_EDGE_BOTH:
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+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
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+ edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_BOTH << gpio);
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+ break;
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+ case IRQ_TYPE_LEVEL_LOW:
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+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
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+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_LOW << gpio);
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+ break;
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+ case IRQ_TYPE_LEVEL_HIGH:
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+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
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+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_HIGH << gpio);
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+ break;
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+ default:
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+ printk(KERN_WARNING "No irq type\n");
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+ spin_unlock_irqrestore(&cchip->lock, flags);
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+ return -EINVAL;
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+ }
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+
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+ __raw_writel(method, cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
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+ __raw_writel(edges, cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
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+ __raw_writel(type, cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
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+ spin_unlock_irqrestore(&cchip->lock, flags);
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+
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+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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+ __irq_set_handler_locked(d->irq, handle_level_irq);
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+ else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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+ __irq_set_handler_locked(d->irq, handle_edge_irq);
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+
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+ return 0;
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+}
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+
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+void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
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+ u32 base, int irq, int secondary_irq_base)
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+{
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+ struct cns3xxx_gpio_chip *cchip;
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+ struct irq_chip_generic *gc;
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+ struct irq_chip_type *ct;
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+ char gc_label[16];
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+
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+ if (cns3xxx_gpio_chip_count == ARRAY_SIZE(cns3xxx_gpio_chips))
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+ return;
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+
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+ snprintf(gc_label, sizeof(gc_label), "cns3xxx_gpio%d",
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+ cns3xxx_gpio_chip_count);
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+
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+ cchip = cns3xxx_gpio_chips + cns3xxx_gpio_chip_count;
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+ cchip->chip.label = kstrdup(gc_label, GFP_KERNEL);
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+ cchip->chip.direction_input = cns3xxx_gpio_direction_input;
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+ cchip->chip.get = cns3xxx_gpio_get;
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+ cchip->chip.direction_output = cns3xxx_gpio_direction_output;
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+ cchip->chip.set = cns3xxx_gpio_set;
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+ cchip->chip.to_irq = cns3xxx_gpio_to_irq;
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+ cchip->chip.base = gpio_base;
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+ cchip->chip.ngpio = ngpio;
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+ cchip->chip.can_sleep = 0;
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+ spin_lock_init(&cchip->lock);
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+ cchip->base = (void __iomem *)base;
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+ cchip->secondary_irq_base = secondary_irq_base;
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+
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+ BUG_ON(gpiochip_add(&cchip->chip) < 0);
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+ cns3xxx_gpio_chip_count++;
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+
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+ /* clear GPIO interrupts */
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+ __raw_writel(0xffff, cchip->base + GPIO_INTERRUPT_CLEAR);
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+
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+ /*
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+ * IRQ chip init
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+ */
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+ gc = irq_alloc_generic_chip("cns3xxx_gpio_irq", 1, secondary_irq_base,
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+ cchip->base, handle_edge_irq);
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+ gc->private = cchip;
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+
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+ ct = gc->chip_types;
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+ ct->type = IRQ_TYPE_EDGE_FALLING;
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+ ct->regs.ack = GPIO_INTERRUPT_CLEAR;
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+ ct->regs.enable = GPIO_INTERRUPT_ENABLE;
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+ ct->chip.irq_ack = irq_gc_ack_set_bit;
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+ ct->chip.irq_enable = irq_gc_unmask_enable_reg;
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+ ct->chip.irq_disable = irq_gc_mask_disable_reg;
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+ ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;
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+ ct->handler = handle_edge_irq;
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+
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+ irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
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+ IRQ_NOREQUEST, 0);
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+
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+ irq_set_chained_handler(irq, cns3xxx_gpio_irq_handler);
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+ irq_set_handler_data(irq, cchip);
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+}
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--- a/arch/arm/mach-cns3xxx/include/mach/gpio.h
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+++ b/arch/arm/mach-cns3xxx/include/mach/gpio.h
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@@ -1,98 +1,17 @@
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/*
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* arch/arm/mach-cns3xxx/include/mach/gpio.h
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*
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- * CNS3xxx GPIO wrappers for arch-neutral GPIO calls
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- *
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- * Copyright 2011 Gateworks Corporation
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- * Chris Lang <clang@gateworks.com>
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- *
|
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- * Based on IXP implementation by Milan Svoboda <msvoboda@ra.rockwell.com>
|
||||
- * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or modify
|
||||
- * it under the terms of the GNU General Public License as published by
|
||||
- * the Free Software Foundation; either version 2 of the License, or
|
||||
- * (at your option) any later version.
|
||||
- *
|
||||
- * This program is distributed in the hope that it will be useful,
|
||||
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
- * GNU General Public License for more details.
|
||||
- *
|
||||
- * You should have received a copy of the GNU General Public License
|
||||
- * along with this program; if not, write to the Free Software
|
||||
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
+ * This file is licensed under the terms of the GNU General Public
|
||||
+ * License version 2. This program is licensed "as is" without any
|
||||
+ * warranty of any kind, whether express or implied.
|
||||
*
|
||||
*/
|
||||
-
|
||||
#ifndef __ASM_ARCH_CNS3XXX_GPIO_H
|
||||
#define __ASM_ARCH_CNS3XXX_GPIO_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
-#include <linux/io.h>
|
||||
-#include <mach/platform.h>
|
||||
-#include <asm-generic/gpio.h> /* cansleep wrappers */
|
||||
-
|
||||
-#define NR_BUILTIN_GPIO 64
|
||||
-
|
||||
-#define CNS3XXX_GPIO_IN 0x0
|
||||
-#define CNS3XXX_GPIO_OUT 0x1
|
||||
-
|
||||
-#define CNS3XXX_GPIO_LO 0
|
||||
-#define CNS3XXX_GPIO_HI 1
|
||||
-
|
||||
-#define CNS3XXX_GPIO_OUTPUT 0x00
|
||||
-#define CNS3XXX_GPIO_INPUT 0x04
|
||||
-#define CNS3XXX_GPIO_DIR 0x08
|
||||
-#define CNS3XXX_GPIO_SET 0x10
|
||||
-#define CNS3XXX_GPIO_CLEAR 0x14
|
||||
-
|
||||
-static inline void gpio_line_get(u8 line, int *value)
|
||||
-{
|
||||
- if (line < 32)
|
||||
- *value = ((__raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> line) & 0x1);
|
||||
- else
|
||||
- *value = ((__raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> (line - 32)) & 0x1);
|
||||
-}
|
||||
-
|
||||
-static inline void gpio_line_set(u8 line, int value)
|
||||
-{
|
||||
- if (line < 32) {
|
||||
- if (value)
|
||||
- __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_SET);
|
||||
- else
|
||||
- __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
|
||||
- } else {
|
||||
- if (value)
|
||||
- __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_SET);
|
||||
- else
|
||||
- __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
|
||||
- }
|
||||
-}
|
||||
-
|
||||
-static inline int gpio_get_value(unsigned gpio)
|
||||
-{
|
||||
- if (gpio < NR_BUILTIN_GPIO)
|
||||
- {
|
||||
- int value;
|
||||
- gpio_line_get(gpio, &value);
|
||||
- return value;
|
||||
- }
|
||||
- else
|
||||
- return __gpio_get_value(gpio);
|
||||
-}
|
||||
-
|
||||
-static inline void gpio_set_value(unsigned gpio, int value)
|
||||
-{
|
||||
- if (gpio < NR_BUILTIN_GPIO)
|
||||
- gpio_line_set(gpio, value);
|
||||
- else
|
||||
- __gpio_set_value(gpio, value);
|
||||
-}
|
||||
-
|
||||
-#define gpio_cansleep __gpio_cansleep
|
||||
|
||||
-extern int gpio_to_irq(int gpio);
|
||||
-extern int irq_to_gpio(int gpio);
|
||||
+extern void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
|
||||
+ u32 base, int irq, int secondary_irq_base);
|
||||
|
||||
#endif
|
||||
--- a/arch/arm/mach-cns3xxx/laguna.c
|
||||
+++ b/arch/arm/mach-cns3xxx/laguna.c
|
||||
@@ -45,6 +45,7 @@
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/platform.h>
|
||||
#include <mach/pm.h>
|
||||
+#include <mach/gpio.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include "core.h"
|
||||
#include "devices.h"
|
||||
@@ -759,6 +760,10 @@ static int __init laguna_model_setup(voi
|
||||
u8 pcie_bitmap = 0;
|
||||
|
||||
printk("Running on Gateworks Laguna %s\n", laguna_info.model);
|
||||
+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
|
||||
+ NR_IRQS_CNS3XXX);
|
||||
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
|
||||
+ NR_IRQS_CNS3XXX + 32);
|
||||
|
||||
if (strncmp(laguna_info.model, "GW", 2) == 0) {
|
||||
if (laguna_info.config_bitmap & ETH0_LOAD)
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -366,7 +366,8 @@ config ARCH_CLPS711X
|
||||
config ARCH_CNS3XXX
|
||||
bool "Cavium Networks CNS3XXX family"
|
||||
select CPU_V6K
|
||||
- select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
+ select ARCH_REQUIRE_GPIOLIB
|
||||
+ select GENERIC_IRQ_CHIP
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select ARM_GIC
|
||||
select CLKDEV_LOOKUP
|
||||
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
|
||||
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
|
||||
@@ -627,7 +627,7 @@ int cns3xxx_cpu_clock(void);
|
||||
|
||||
#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
|
||||
#undef NR_IRQS
|
||||
-#define NR_IRQS NR_IRQS_CNS3XXX
|
||||
+#define NR_IRQS (NR_IRQS_CNS3XXX + 64)
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_BOARD_CNS3XXX_H */
|
Loading…
Reference in new issue