Mathias Kresin
7 years ago
parent
e0d6f541f7
commit
6b06c2fb8e
@ -1,204 +0,0 @@ |
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CONFIG_ARCH_BINFMT_ELF_STATE=y |
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CONFIG_ARCH_CLOCKSOURCE_DATA=y |
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CONFIG_ARCH_DISCARD_MEMBLOCK=y |
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CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y |
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CONFIG_ARCH_HAS_ELF_RANDOMIZE=y |
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# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set |
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CONFIG_ARCH_HAS_RESET_CONTROLLER=y |
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# CONFIG_ARCH_HAS_SG_CHAIN is not set |
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y |
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y |
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CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y |
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CONFIG_ARCH_REQUIRE_GPIOLIB=y |
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CONFIG_ARCH_SUPPORTS_UPROBES=y |
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CONFIG_ARCH_SUSPEND_POSSIBLE=y |
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CONFIG_ARCH_USE_BUILTIN_BSWAP=y |
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y |
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CONFIG_CEVT_R4K=y |
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CONFIG_CLKDEV_LOOKUP=y |
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CONFIG_CLONE_BACKWARDS=y |
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CONFIG_CPU_BIG_ENDIAN=y |
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CONFIG_CPU_GENERIC_DUMP_TLB=y |
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CONFIG_CPU_HAS_PREFETCH=y |
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CONFIG_CPU_HAS_SYNC=y |
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CONFIG_CPU_MIPS32=y |
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# CONFIG_CPU_MIPS32_R1 is not set |
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CONFIG_CPU_MIPS32_R2=y |
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CONFIG_CPU_MIPSR2=y |
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CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y |
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CONFIG_CPU_R4K_CACHE_TLB=y |
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CONFIG_CPU_R4K_FPU=y |
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y |
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CONFIG_CPU_SUPPORTS_HIGHMEM=y |
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CONFIG_CPU_SUPPORTS_MSA=y |
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CONFIG_CRYPTO_HASH=y |
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CONFIG_CRYPTO_HASH2=y |
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CONFIG_CRYPTO_RNG2=y |
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CONFIG_CRYPTO_WORKQUEUE=y |
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CONFIG_CSRC_R4K=y |
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CONFIG_DMA_NONCOHERENT=y |
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CONFIG_DTC=y |
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# CONFIG_DT_EASY50712 is not set |
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CONFIG_EARLY_PRINTK=y |
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CONFIG_ETHERNET_PACKET_MANGLE=y |
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CONFIG_GENERIC_ATOMIC64=y |
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CONFIG_GENERIC_CLOCKEVENTS=y |
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CONFIG_GENERIC_CMOS_UPDATE=y |
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CONFIG_GENERIC_IO=y |
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CONFIG_GENERIC_IRQ_CHIP=y |
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CONFIG_GENERIC_IRQ_SHOW=y |
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CONFIG_GENERIC_PCI_IOMAP=y |
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CONFIG_GENERIC_SCHED_CLOCK=y |
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CONFIG_GENERIC_SMP_IDLE_THREAD=y |
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CONFIG_GENERIC_TIME_VSYSCALL=y |
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CONFIG_GPIOLIB=y |
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CONFIG_GPIO_DEVRES=y |
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CONFIG_GPIO_MM_LANTIQ=y |
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CONFIG_GPIO_STP_XWAY=y |
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CONFIG_GPIO_SYSFS=y |
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CONFIG_HARDWARE_WATCHPOINTS=y |
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CONFIG_HAS_DMA=y |
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CONFIG_HAS_IOMEM=y |
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CONFIG_HAS_IOPORT_MAP=y |
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# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set |
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# CONFIG_HAVE_ARCH_BITREVERSE is not set |
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CONFIG_HAVE_ARCH_JUMP_LABEL=y |
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CONFIG_HAVE_ARCH_KGDB=y |
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CONFIG_HAVE_ARCH_SECCOMP_FILTER=y |
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CONFIG_HAVE_ARCH_TRACEHOOK=y |
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# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set |
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CONFIG_HAVE_BPF_JIT=y |
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CONFIG_HAVE_CC_STACKPROTECTOR=y |
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CONFIG_HAVE_CLK=y |
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CONFIG_HAVE_CONTEXT_TRACKING=y |
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CONFIG_HAVE_C_RECORDMCOUNT=y |
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CONFIG_HAVE_DEBUG_KMEMLEAK=y |
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CONFIG_HAVE_DEBUG_STACKOVERFLOW=y |
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CONFIG_HAVE_DMA_API_DEBUG=y |
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CONFIG_HAVE_DMA_ATTRS=y |
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CONFIG_HAVE_DMA_CONTIGUOUS=y |
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CONFIG_HAVE_DYNAMIC_FTRACE=y |
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y |
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y |
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CONFIG_HAVE_FUNCTION_TRACER=y |
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
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CONFIG_HAVE_IDE=y |
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CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y |
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CONFIG_HAVE_KVM=y |
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CONFIG_HAVE_LATENCYTOP_SUPPORT=y |
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CONFIG_HAVE_MACH_CLKDEV=y |
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CONFIG_HAVE_MEMBLOCK=y |
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CONFIG_HAVE_MEMBLOCK_NODE_MAP=y |
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CONFIG_HAVE_MOD_ARCH_SPECIFIC=y |
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CONFIG_HAVE_NET_DSA=y |
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CONFIG_HAVE_OPROFILE=y |
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CONFIG_HAVE_PERF_EVENTS=y |
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y |
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CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y |
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CONFIG_HW_HAS_PCI=y |
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CONFIG_HW_RANDOM=y |
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CONFIG_HZ=250 |
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# CONFIG_HZ_100 is not set |
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CONFIG_HZ_250=y |
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CONFIG_HZ_PERIODIC=y |
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CONFIG_INITRAMFS_SOURCE="" |
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CONFIG_IRQCHIP=y |
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CONFIG_IRQ_DOMAIN=y |
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CONFIG_IRQ_FORCED_THREADING=y |
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CONFIG_IRQ_MIPS_CPU=y |
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CONFIG_IRQ_WORK=y |
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CONFIG_LANTIQ=y |
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CONFIG_LANTIQ_DT_NONE=y |
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CONFIG_LANTIQ_ETOP=y |
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CONFIG_LANTIQ_WDT=y |
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# CONFIG_LANTIQ_XRX200 is not set |
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CONFIG_LEDS_GPIO=y |
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CONFIG_LIBFDT=y |
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CONFIG_MDIO_BOARDINFO=y |
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CONFIG_MIPS=y |
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CONFIG_MIPS_CLOCK_VSYSCALL=y |
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# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set |
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# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set |
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CONFIG_MIPS_CMDLINE_FROM_DTB=y |
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# CONFIG_MIPS_ELF_APPENDED_DTB is not set |
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# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set |
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CONFIG_MIPS_L1_CACHE_SHIFT=5 |
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# CONFIG_MIPS_MACHINE is not set |
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# CONFIG_MIPS_MT_SMP is not set |
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# CONFIG_MIPS_NO_APPENDED_DTB is not set |
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CONFIG_MIPS_RAW_APPENDED_DTB=y |
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CONFIG_MIPS_SPRAM=y |
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# CONFIG_MIPS_VPE_LOADER is not set |
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CONFIG_MODULES_USE_ELF_REL=y |
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CONFIG_MTD_CFI_ADV_OPTIONS=y |
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CONFIG_MTD_CFI_GEOMETRY=y |
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CONFIG_MTD_CMDLINE_PARTS=y |
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CONFIG_MTD_JEDECPROBE=y |
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CONFIG_MTD_LANTIQ=y |
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CONFIG_MTD_M25P80=y |
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CONFIG_MTD_SPI_NOR=y |
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CONFIG_MTD_SPLIT_BRNIMAGE_FW=y |
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CONFIG_MTD_SPLIT_EVA_FW=y |
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CONFIG_MTD_SPLIT_FIRMWARE=y |
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CONFIG_MTD_SPLIT_TPLINK_FW=y |
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CONFIG_MTD_SPLIT_UIMAGE_FW=y |
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CONFIG_NEED_DMA_MAP_STATE=y |
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CONFIG_NEED_PER_CPU_KM=y |
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CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y |
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# CONFIG_NO_IOPORT_MAP is not set |
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CONFIG_OF=y |
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CONFIG_OF_ADDRESS=y |
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CONFIG_OF_ADDRESS_PCI=y |
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CONFIG_OF_EARLY_FLATTREE=y |
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CONFIG_OF_FLATTREE=y |
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CONFIG_OF_GPIO=y |
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CONFIG_OF_IRQ=y |
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CONFIG_OF_MDIO=y |
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CONFIG_OF_MTD=y |
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CONFIG_OF_NET=y |
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CONFIG_OF_PCI=y |
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CONFIG_OF_PCI_IRQ=y |
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CONFIG_PCI=y |
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# CONFIG_PCIE_LANTIQ is not set |
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CONFIG_PCI_DOMAINS=y |
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CONFIG_PCI_LANTIQ=y |
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CONFIG_PERF_USE_VMALLOC=y |
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CONFIG_PGTABLE_LEVELS=2 |
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CONFIG_PHYLIB=y |
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CONFIG_PINCTRL=y |
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CONFIG_PINCTRL_LANTIQ=y |
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# CONFIG_PINCTRL_SINGLE is not set |
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CONFIG_PINCTRL_XWAY=y |
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CONFIG_PSB6970_PHY=y |
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# CONFIG_RCU_STALL_COMMON is not set |
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CONFIG_RESET_CONTROLLER=y |
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CONFIG_RTL8366RB_PHY=y |
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CONFIG_RTL8366_SMI=y |
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# CONFIG_SCHED_INFO is not set |
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# CONFIG_SCSI_DMA is not set |
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# CONFIG_SENSORS_LTQ_CPUTEMP is not set |
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# CONFIG_SERIAL_8250 is not set |
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CONFIG_SERIAL_LANTIQ=y |
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# CONFIG_SOC_AMAZON_SE is not set |
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# CONFIG_SOC_FALCON is not set |
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CONFIG_SOC_TYPE_XWAY=y |
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CONFIG_SOC_XWAY=y |
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CONFIG_SPI=y |
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CONFIG_SPI_LANTIQ=y |
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CONFIG_SPI_MASTER=y |
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CONFIG_SRCU=y |
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CONFIG_SWAP_IO_SPACE=y |
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CONFIG_SWCONFIG=y |
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CONFIG_SYSCTL_EXCEPTION_TRACE=y |
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y |
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CONFIG_SYS_HAS_CPU_MIPS32_R2=y |
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CONFIG_SYS_HAS_EARLY_PRINTK=y |
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y |
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y |
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CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y |
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CONFIG_SYS_SUPPORTS_MIPS16=y |
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CONFIG_SYS_SUPPORTS_MULTITHREADING=y |
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CONFIG_TICK_CPU_ACCOUNTING=y |
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CONFIG_USE_OF=y |
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# CONFIG_XRX200_PHY_FW is not set |
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CONFIG_ZONE_DMA_FLAG=0 |
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File diff suppressed because it is too large
Load Diff
@ -1,500 +0,0 @@ |
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From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 3 Aug 2012 10:27:25 +0200
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Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++
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arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++
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arch/mips/lantiq/irq.c | 2 +
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arch/mips/mm/cache.c | 2 +
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include/uapi/linux/atm.h | 6 +
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net/atm/common.c | 6 +
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net/atm/proc.c | 2 +-
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7 files changed, 416 insertions(+), 1 deletion(-)
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create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
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create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
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@@ -0,0 +1,196 @@
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+/******************************************************************************
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+**
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+** FILE NAME : ifx_atm.h
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+** PROJECT : UEIP
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+** MODULES : ATM
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+**
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+** DATE : 17 Jun 2009
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+** AUTHOR : Xu Liang
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+** DESCRIPTION : Global ATM driver header file
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+** COPYRIGHT : Copyright (c) 2006
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+** Infineon Technologies AG
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+** Am Campeon 1-12, 85579 Neubiberg, Germany
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+**
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+** This program is free software; you can redistribute it and/or modify
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+** it under the terms of the GNU General Public License as published by
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+** the Free Software Foundation; either version 2 of the License, or
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+** (at your option) any later version.
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+**
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+** HISTORY
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+** $Date $Author $Comment
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+** 07 JUL 2009 Xu Liang Init Version
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+*******************************************************************************/
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+
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+#ifndef IFX_ATM_H
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+#define IFX_ATM_H
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+
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+
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+
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+/*!
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+ \defgroup IFX_ATM UEIP Project - ATM driver module
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+ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
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+ */
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+
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+/*!
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+ \defgroup IFX_ATM_IOCTL IOCTL Commands
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+ \ingroup IFX_ATM
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+ \brief IOCTL Commands used by user application.
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+ */
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+
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+/*!
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+ \defgroup IFX_ATM_STRUCT Structures
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+ \ingroup IFX_ATM
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+ \brief Structures used by user application.
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+ */
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+
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+/*!
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+ \file ifx_atm.h
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+ \ingroup IFX_ATM
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+ \brief ATM driver header file
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+ */
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+
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+
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+
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+/*
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+ * ####################################
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+ * Definition
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+ * ####################################
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+ */
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+
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+/*!
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+ \addtogroup IFX_ATM_STRUCT
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+ */
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+/*@{*/
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+
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+/*
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+ * ATM MIB
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+ */
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+
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+/*!
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+ \struct atm_cell_ifEntry_t
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+ \brief Structure used for Cell Level MIB Counters.
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+
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+ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
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+ */
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+typedef struct {
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+ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
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+ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
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+ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
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+ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
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+ __u32 ifInErrors; /*!< counter of error ingress cells */
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+ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
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+ __u32 ifOutErrors; /*!< counter of error egress cells */
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+} atm_cell_ifEntry_t;
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+
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+/*!
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+ \struct atm_aal5_ifEntry_t
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+ \brief Structure used for AAL5 Frame Level MIB Counters.
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+
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+ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
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+ */
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+typedef struct {
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+ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
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+ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
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+ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
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+ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
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+ __u32 ifInUcastPkts; /*!< counter of ingress packets */
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+ __u32 ifOutUcastPkts; /*!< counter of egress packets */
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+ __u32 ifInErrors; /*!< counter of error ingress packets */
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+ __u32 ifInDiscards; /*!< counter of dropped ingress packets */
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+ __u32 ifOutErros; /*!< counter of error egress packets */
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+ __u32 ifOutDiscards; /*!< counter of dropped egress packets */
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+} atm_aal5_ifEntry_t;
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+
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+/*!
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+ \struct atm_aal5_vcc_t
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+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
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+
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+ This structure is a part of structure "atm_aal5_vcc_x_t".
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+ */
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+typedef struct {
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+ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
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+ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
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+ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
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+} atm_aal5_vcc_t;
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+
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+/*!
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+ \struct atm_aal5_vcc_x_t
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+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
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+
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+ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
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+ */
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+typedef struct {
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+ int vpi; /*!< VPI of the VCC to get MIB counters */
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+ int vci; /*!< VCI of the VCC to get MIB counters */
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+ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
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+} atm_aal5_vcc_x_t;
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+
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+/*@}*/
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+
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+
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+
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+/*
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+ * ####################################
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+ * IOCTL
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+ * ####################################
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+ */
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+
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+/*!
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+ \addtogroup IFX_ATM_IOCTL
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+ */
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+/*@{*/
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+
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+/*
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+ * ioctl Command
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+ */
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+/*!
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+ \brief ATM IOCTL Magic Number
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+ */
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+#define PPE_ATM_IOC_MAGIC 'o'
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+/*!
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+ \brief ATM IOCTL Command - Get Cell Level MIB Counters
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+
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+ This command is obsolete. User can get cell level MIB from DSL API.
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+ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
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+ */
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+#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
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+/*!
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+ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
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+
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+ Get AAL5 packet counters.
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+ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
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+ */
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+#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
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+/*!
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+ \brief ATM IOCTL Command - Get Per PVC MIB Counters
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+
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+ Get AAL5 packet counters for each PVC.
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+ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
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+ */
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+#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
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+/*!
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+ \brief Total Number of ATM IOCTL Commands
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+ */
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+#define PPE_ATM_IOC_MAXNR 3
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+
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+/*@}*/
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+
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+
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+
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+/*
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+ * ####################################
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+ * API
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+ * ####################################
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+ */
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+
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+#ifdef __KERNEL__
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+struct port_cell_info {
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+ unsigned int port_num;
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+ unsigned int tx_link_rate[2];
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+};
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+#endif
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+
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+
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+
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+#endif // IFX_ATM_H
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+
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
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@@ -0,0 +1,203 @@
|
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+/******************************************************************************
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+**
|
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+** FILE NAME : ifx_ptm.h
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+** PROJECT : UEIP
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+** MODULES : PTM
|
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+**
|
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+** DATE : 17 Jun 2009
|
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+** AUTHOR : Xu Liang
|
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+** DESCRIPTION : Global PTM driver header file
|
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+** COPYRIGHT : Copyright (c) 2006
|
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+** Infineon Technologies AG
|
||||
+** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
+**
|
||||
+** This program is free software; you can redistribute it and/or modify
|
||||
+** it under the terms of the GNU General Public License as published by
|
||||
+** the Free Software Foundation; either version 2 of the License, or
|
||||
+** (at your option) any later version.
|
||||
+**
|
||||
+** HISTORY
|
||||
+** $Date $Author $Comment
|
||||
+** 07 JUL 2009 Xu Liang Init Version
|
||||
+*******************************************************************************/
|
||||
+
|
||||
+#ifndef IFX_PTM_H
|
||||
+#define IFX_PTM_H
|
||||
+
|
||||
+
|
||||
+
|
||||
+/*!
|
||||
+ \defgroup IFX_PTM UEIP Project - PTM driver module
|
||||
+ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
|
||||
+ */
|
||||
+
|
||||
+/*!
|
||||
+ \defgroup IFX_PTM_IOCTL IOCTL Commands
|
||||
+ \ingroup IFX_PTM
|
||||
+ \brief IOCTL Commands used by user application.
|
||||
+ */
|
||||
+
|
||||
+/*!
|
||||
+ \defgroup IFX_PTM_STRUCT Structures
|
||||
+ \ingroup IFX_PTM
|
||||
+ \brief Structures used by user application.
|
||||
+ */
|
||||
+
|
||||
+/*!
|
||||
+ \file ifx_ptm.h
|
||||
+ \ingroup IFX_PTM
|
||||
+ \brief PTM driver header file
|
||||
+ */
|
||||
+
|
||||
+
|
||||
+
|
||||
+/*
|
||||
+ * ####################################
|
||||
+ * Definition
|
||||
+ * ####################################
|
||||
+ */
|
||||
+
|
||||
+
|
||||
+
|
||||
+/*
|
||||
+ * ####################################
|
||||
+ * IOCTL
|
||||
+ * ####################################
|
||||
+ */
|
||||
+
|
||||
+/*!
|
||||
+ \addtogroup IFX_PTM_IOCTL
|
||||
+ */
|
||||
+/*@{*/
|
||||
+
|
||||
+/*
|
||||
+ * ioctl Command
|
||||
+ */
|
||||
+/*!
|
||||
+ \brief PTM IOCTL Command - Get codeword MIB counters.
|
||||
+
|
||||
+ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
|
||||
+ */
|
||||
+#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1
|
||||
+/*!
|
||||
+ \brief PTM IOCTL Command - Get packet MIB counters.
|
||||
+
|
||||
+ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
|
||||
+ */
|
||||
+#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2
|
||||
+/*!
|
||||
+ \brief PTM IOCTL Command - Get firmware configuration (CRC).
|
||||
+
|
||||
+ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
|
||||
+ */
|
||||
+#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3
|
||||
+/*!
|
||||
+ \brief PTM IOCTL Command - Set firmware configuration (CRC).
|
||||
+
|
||||
+ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
|
||||
+ */
|
||||
+#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4
|
||||
+/*!
|
||||
+ \brief PTM IOCTL Command - Program priority value to TX queue mapping.
|
||||
+
|
||||
+ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
|
||||
+ */
|
||||
+#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14
|
||||
+
|
||||
+/*@}*/
|
||||
+
|
||||
+
|
||||
+/*!
|
||||
+ \addtogroup IFX_PTM_STRUCT
|
||||
+ */
|
||||
+/*@{*/
|
||||
+
|
||||
+/*
|
||||
+ * ioctl Data Type
|
||||
+ */
|
||||
+
|
||||
+/*!
|
||||
+ \typedef PTM_CW_IF_ENTRY_T
|
||||
+ \brief Wrapping of structure "ptm_cw_ifEntry_t".
|
||||
+ */
|
||||
+/*!
|
||||
+ \struct ptm_cw_ifEntry_t
|
||||
+ \brief Structure used for CodeWord level MIB counters.
|
||||
+ */
|
||||
+typedef struct ptm_cw_ifEntry_t {
|
||||
+ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */
|
||||
+ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */
|
||||
+ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */
|
||||
+ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */
|
||||
+ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */
|
||||
+} PTM_CW_IF_ENTRY_T;
|
||||
+
|
||||
+/*!
|
||||
+ \typedef PTM_FRAME_MIB_T
|
||||
+ \brief Wrapping of structure "ptm_frame_mib_t".
|
||||
+ */
|
||||
+/*!
|
||||
+ \struct ptm_frame_mib_t
|
||||
+ \brief Structure used for packet level MIB counters.
|
||||
+ */
|
||||
+typedef struct ptm_frame_mib_t {
|
||||
+ uint32_t RxCorrect; /*!< output, number of ingress packet */
|
||||
+ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */
|
||||
+ uint32_t RxDropped; /*!< output, number of dropped ingress packet */
|
||||
+ uint32_t TxSend; /*!< output, number of egress packet */
|
||||
+} PTM_FRAME_MIB_T;
|
||||
+
|
||||
+/*!
|
||||
+ \typedef IFX_PTM_CFG_T
|
||||
+ \brief Wrapping of structure "ptm_cfg_t".
|
||||
+ */
|
||||
+/*!
|
||||
+ \struct ptm_cfg_t
|
||||
+ \brief Structure used for ETH/TC CRC configuration.
|
||||
+ */
|
||||
+typedef struct ptm_cfg_t {
|
||||
+ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */
|
||||
+ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */
|
||||
+ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */
|
||||
+ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */
|
||||
+ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */
|
||||
+ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */
|
||||
+ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */
|
||||
+} IFX_PTM_CFG_T;
|
||||
+
|
||||
+/*!
|
||||
+ \typedef IFX_PTM_PRIO_Q_MAP_T
|
||||
+ \brief Wrapping of structure "ppe_prio_q_map".
|
||||
+ */
|
||||
+/*!
|
||||
+ \struct ppe_prio_q_map
|
||||
+ \brief Structure used for Priority Value to TX Queue mapping.
|
||||
+ */
|
||||
+typedef struct ppe_prio_q_map {
|
||||
+ int pkt_prio;
|
||||
+ int qid;
|
||||
+ int vpi; // ignored in eth interface
|
||||
+ int vci; // ignored in eth interface
|
||||
+} IFX_PTM_PRIO_Q_MAP_T;
|
||||
+
|
||||
+/*@}*/
|
||||
+
|
||||
+
|
||||
+
|
||||
+/*
|
||||
+ * ####################################
|
||||
+ * API
|
||||
+ * ####################################
|
||||
+ */
|
||||
+
|
||||
+#ifdef __KERNEL__
|
||||
+struct port_cell_info {
|
||||
+ unsigned int port_num;
|
||||
+ unsigned int tx_link_rate[2];
|
||||
+};
|
||||
+#endif
|
||||
+
|
||||
+
|
||||
+
|
||||
+#endif // IFX_PTM_H
|
||||
+
|
||||
--- a/arch/mips/lantiq/irq.c
|
||||
+++ b/arch/mips/lantiq/irq.c
|
||||
@@ -14,6 +14,7 @@
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
+#include <linux/module.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
@@ -100,6 +101,7 @@ void ltq_mask_and_ack_irq(struct irq_dat
|
||||
ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
|
||||
ltq_icu_w32(im, BIT(offset), isr);
|
||||
}
|
||||
+EXPORT_SYMBOL(ltq_mask_and_ack_irq);
|
||||
|
||||
static void ltq_ack_irq(struct irq_data *d)
|
||||
{
|
||||
--- a/arch/mips/mm/cache.c
|
||||
+++ b/arch/mips/mm/cache.c
|
||||
@@ -59,6 +59,8 @@ void (*_dma_cache_wback)(unsigned long s
|
||||
void (*_dma_cache_inv)(unsigned long start, unsigned long size);
|
||||
|
||||
EXPORT_SYMBOL(_dma_cache_wback_inv);
|
||||
+EXPORT_SYMBOL(_dma_cache_wback);
|
||||
+EXPORT_SYMBOL(_dma_cache_inv);
|
||||
|
||||
#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
|
||||
|
||||
--- a/include/uapi/linux/atm.h
|
||||
+++ b/include/uapi/linux/atm.h
|
||||
@@ -130,8 +130,14 @@
|
||||
#define ATM_ABR 4
|
||||
#define ATM_ANYCLASS 5 /* compatible with everything */
|
||||
|
||||
+#define ATM_VBR_NRT ATM_VBR
|
||||
+#define ATM_VBR_RT 6
|
||||
+#define ATM_UBR_PLUS 7
|
||||
+#define ATM_GFR 8
|
||||
+
|
||||
#define ATM_MAX_PCR -1 /* maximum available PCR */
|
||||
|
||||
+
|
||||
struct atm_trafprm {
|
||||
unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
|
||||
int max_pcr; /* maximum PCR in cells per second */
|
||||
--- a/net/atm/common.c
|
||||
+++ b/net/atm/common.c
|
||||
@@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc
|
||||
write_unlock_irq(&vcc_sklist_lock);
|
||||
}
|
||||
|
||||
+struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
|
||||
+EXPORT_SYMBOL(ifx_atm_alloc_tx);
|
||||
+
|
||||
static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
|
||||
{
|
||||
struct sk_buff *skb;
|
||||
struct sock *sk = sk_atm(vcc);
|
||||
|
||||
+ if (ifx_atm_alloc_tx != NULL)
|
||||
+ return ifx_atm_alloc_tx(vcc, size);
|
||||
+
|
||||
if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
|
||||
pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
|
||||
sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
|
||||
--- a/net/atm/proc.c
|
||||
+++ b/net/atm/proc.c
|
||||
@@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil
|
||||
static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
|
||||
{
|
||||
static const char *const class_name[] = {
|
||||
- "off", "UBR", "CBR", "VBR", "ABR"};
|
||||
+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
|
||||
static const char *const aal_name[] = {
|
||||
"---", "1", "2", "3/4", /* 0- 3 */
|
||||
"???", "5", "???", "???", /* 4- 7 */
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,68 +0,0 @@ |
||||
From 25494c55a4007a1409f53ddbafd661636e47ea34 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 9 Aug 2013 20:38:15 +0200
|
||||
Subject: [PATCH 12/36] pinctrl/lantiq: fix up pinmux
|
||||
|
||||
We found out how to set the gphy led pinmuxing.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/pinctrl/pinctrl-xway.c | 28 ++++++++++++++++++++++++++--
|
||||
1 file changed, 26 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/pinctrl/pinctrl-xway.c
|
||||
+++ b/drivers/pinctrl/pinctrl-xway.c
|
||||
@@ -609,10 +609,9 @@ static struct pinctrl_desc xway_pctrl_de
|
||||
.confops = &xway_pinconf_ops,
|
||||
};
|
||||
|
||||
-static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
|
||||
+static int mux_apply(struct ltq_pinmux_info *info,
|
||||
int pin, int mux)
|
||||
{
|
||||
- struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
|
||||
int port = PORT(pin);
|
||||
u32 alt1_reg = GPIO_ALT1(pin);
|
||||
|
||||
@@ -632,6 +631,14 @@ static inline int xway_mux_apply(struct
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
|
||||
+ int pin, int mux)
|
||||
+{
|
||||
+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
|
||||
+
|
||||
+ return mux_apply(info, pin, mux);
|
||||
+}
|
||||
+
|
||||
static const struct ltq_cfg_param xway_cfg_params[] = {
|
||||
{"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
|
||||
{"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
|
||||
@@ -682,6 +689,18 @@ static int xway_gpio_dir_out(struct gpio
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
||||
+{
|
||||
+ struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < info->num_exin; i++)
|
||||
+ if (info->exin[i] == offset)
|
||||
+ return ltq_eiu_get_irq(i);
|
||||
+
|
||||
+ return -1;
|
||||
+}
|
||||
+
|
||||
static struct gpio_chip xway_chip = {
|
||||
.label = "gpio-xway",
|
||||
.direction_input = xway_gpio_dir_in,
|
||||
@@ -690,6 +709,7 @@ static struct gpio_chip xway_chip = {
|
||||
.set = xway_gpio_set,
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
+ .to_irq = xway_gpio_to_irq,
|
||||
.base = -1,
|
||||
};
|
||||
|
||||
@ -1,24 +0,0 @@ |
||||
From 8e34da603f442624bb70e887d8f42064bb924224 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 28 Jul 2013 18:03:54 +0200
|
||||
Subject: [PATCH 13/36] MTD: lantiq: xway: fix invalid operator
|
||||
|
||||
xway_read_byte should use a logic or and not an add operator when working out
|
||||
the nand address.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/mtd/nand/xway_nand.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mtd/nand/xway_nand.c
|
||||
+++ b/drivers/mtd/nand/xway_nand.c
|
||||
@@ -124,7 +124,7 @@ static unsigned char xway_read_byte(stru
|
||||
int ret;
|
||||
|
||||
spin_lock_irqsave(&ebu_lock, flags);
|
||||
- ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA));
|
||||
+ ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
|
||||
spin_unlock_irqrestore(&ebu_lock, flags);
|
||||
|
||||
return ret;
|
||||
@ -1,44 +0,0 @@ |
||||
From b454cefd675fc1bd3d8c690c1bd1d8f4678e9922 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 28 Jul 2013 18:06:39 +0200
|
||||
Subject: [PATCH 14/36] MTD: lantiq: xway: the latched command should be
|
||||
persistent
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/mtd/nand/xway_nand.c | 12 ++++++------
|
||||
1 file changed, 6 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/mtd/nand/xway_nand.c
|
||||
+++ b/drivers/mtd/nand/xway_nand.c
|
||||
@@ -54,6 +54,8 @@
|
||||
#define NAND_CON_CSMUX (1 << 1)
|
||||
#define NAND_CON_NANDM 1
|
||||
|
||||
+static u32 xway_latchcmd;
|
||||
+
|
||||
static void xway_reset_chip(struct nand_chip *chip)
|
||||
{
|
||||
unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
|
||||
@@ -94,17 +96,15 @@ static void xway_cmd_ctrl(struct mtd_inf
|
||||
unsigned long flags;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
- nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
|
||||
if (ctrl & NAND_CLE)
|
||||
- nandaddr |= NAND_WRITE_CMD;
|
||||
- else
|
||||
- nandaddr |= NAND_WRITE_ADDR;
|
||||
- this->IO_ADDR_W = (void __iomem *) nandaddr;
|
||||
+ xway_latchcmd = NAND_WRITE_CMD;
|
||||
+ else if (ctrl & NAND_ALE)
|
||||
+ xway_latchcmd = NAND_WRITE_ADDR;
|
||||
}
|
||||
|
||||
if (cmd != NAND_CMD_NONE) {
|
||||
spin_lock_irqsave(&ebu_lock, flags);
|
||||
- writeb(cmd, this->IO_ADDR_W);
|
||||
+ writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
|
||||
while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
|
||||
;
|
||||
spin_unlock_irqrestore(&ebu_lock, flags);
|
||||
@ -1,41 +0,0 @@ |
||||
From 76e153079f02d26e3357302d2886a0c8aaaec64d Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 28 Jul 2013 18:02:06 +0200
|
||||
Subject: [PATCH 15/36] MTD: lantiq: xway: remove endless loop
|
||||
|
||||
The reset loop logic could run into a endless loop. Lets fix it as requested.
|
||||
|
||||
--> http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/mtd/nand/xway_nand.c | 10 ++++++++--
|
||||
1 file changed, 8 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/mtd/nand/xway_nand.c
|
||||
+++ b/drivers/mtd/nand/xway_nand.c
|
||||
@@ -59,16 +59,22 @@ static u32 xway_latchcmd;
|
||||
static void xway_reset_chip(struct nand_chip *chip)
|
||||
{
|
||||
unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
|
||||
+ unsigned long timeout;
|
||||
unsigned long flags;
|
||||
|
||||
nandaddr &= ~NAND_WRITE_ADDR;
|
||||
nandaddr |= NAND_WRITE_CMD;
|
||||
|
||||
/* finish with a reset */
|
||||
+ timeout = jiffies + msecs_to_jiffies(20);
|
||||
+
|
||||
spin_lock_irqsave(&ebu_lock, flags);
|
||||
writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
|
||||
- while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
|
||||
- ;
|
||||
+ do {
|
||||
+ if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
|
||||
+ break;
|
||||
+ cond_resched();
|
||||
+ } while (!time_after_eq(jiffies, timeout));
|
||||
spin_unlock_irqrestore(&ebu_lock, flags);
|
||||
}
|
||||
|
||||
@ -1,55 +0,0 @@ |
||||
From 65df9d63eaee02c25e879b33dd42aceb78e57842 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 28 Jul 2013 17:59:51 +0200
|
||||
Subject: [PATCH 16/36] MTD: lantiq: xway: add missing write_buf and read_buf
|
||||
to nand driver
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/mtd/nand/xway_nand.c | 28 ++++++++++++++++++++++++++++
|
||||
1 file changed, 28 insertions(+)
|
||||
|
||||
--- a/drivers/mtd/nand/xway_nand.c
|
||||
+++ b/drivers/mtd/nand/xway_nand.c
|
||||
@@ -136,6 +136,32 @@ static unsigned char xway_read_byte(stru
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static void xway_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
||||
+{
|
||||
+ struct nand_chip *this = mtd->priv;
|
||||
+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
|
||||
+ unsigned long flags;
|
||||
+ int i;
|
||||
+
|
||||
+ spin_lock_irqsave(&ebu_lock, flags);
|
||||
+ for (i = 0; i < len; i++)
|
||||
+ buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
|
||||
+ spin_unlock_irqrestore(&ebu_lock, flags);
|
||||
+}
|
||||
+
|
||||
+static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
+{
|
||||
+ struct nand_chip *this = mtd->priv;
|
||||
+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
|
||||
+ unsigned long flags;
|
||||
+ int i;
|
||||
+
|
||||
+ spin_lock_irqsave(&ebu_lock, flags);
|
||||
+ for (i = 0; i < len; i++)
|
||||
+ ltq_w8(buf[i], (void __iomem *)(nandaddr | NAND_WRITE_DATA));
|
||||
+ spin_unlock_irqrestore(&ebu_lock, flags);
|
||||
+}
|
||||
+
|
||||
static int xway_nand_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct nand_chip *this = platform_get_drvdata(pdev);
|
||||
@@ -177,6 +203,8 @@ static struct platform_nand_data xway_na
|
||||
.dev_ready = xway_dev_ready,
|
||||
.select_chip = xway_select_chip,
|
||||
.read_byte = xway_read_byte,
|
||||
+ .read_buf = xway_read_buf,
|
||||
+ .write_buf = xway_write_buf,
|
||||
}
|
||||
};
|
||||
|
||||
@ -1,89 +0,0 @@ |
||||
From aa705c1b0860da91f2ed1a4c0b57337e6de689e1 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 7 Aug 2014 18:55:31 +0200
|
||||
Subject: [PATCH 17/36] MTD: xway: fix nand locking
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/mtd/nand/xway_nand.c | 15 +++------------
|
||||
1 file changed, 3 insertions(+), 12 deletions(-)
|
||||
|
||||
--- a/drivers/mtd/nand/xway_nand.c
|
||||
+++ b/drivers/mtd/nand/xway_nand.c
|
||||
@@ -80,13 +80,16 @@ static void xway_reset_chip(struct nand_
|
||||
|
||||
static void xway_select_chip(struct mtd_info *mtd, int chip)
|
||||
{
|
||||
+ static unsigned long csflags;
|
||||
|
||||
switch (chip) {
|
||||
case -1:
|
||||
ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
|
||||
ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
|
||||
+ spin_unlock_irqrestore(&ebu_lock, csflags);
|
||||
break;
|
||||
case 0:
|
||||
+ spin_lock_irqsave(&ebu_lock, csflags);
|
||||
ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
|
||||
ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
|
||||
break;
|
||||
@@ -99,7 +102,6 @@ static void xway_cmd_ctrl(struct mtd_inf
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
|
||||
- unsigned long flags;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
if (ctrl & NAND_CLE)
|
||||
@@ -109,11 +111,9 @@ static void xway_cmd_ctrl(struct mtd_inf
|
||||
}
|
||||
|
||||
if (cmd != NAND_CMD_NONE) {
|
||||
- spin_lock_irqsave(&ebu_lock, flags);
|
||||
writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
|
||||
while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
|
||||
;
|
||||
- spin_unlock_irqrestore(&ebu_lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -126,12 +126,9 @@ static unsigned char xway_read_byte(stru
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
|
||||
- unsigned long flags;
|
||||
int ret;
|
||||
|
||||
- spin_lock_irqsave(&ebu_lock, flags);
|
||||
ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
|
||||
- spin_unlock_irqrestore(&ebu_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -140,26 +137,20 @@ static void xway_read_buf(struct mtd_inf
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
|
||||
- unsigned long flags;
|
||||
int i;
|
||||
|
||||
- spin_lock_irqsave(&ebu_lock, flags);
|
||||
for (i = 0; i < len; i++)
|
||||
buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
|
||||
- spin_unlock_irqrestore(&ebu_lock, flags);
|
||||
}
|
||||
|
||||
static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
|
||||
- unsigned long flags;
|
||||
int i;
|
||||
|
||||
- spin_lock_irqsave(&ebu_lock, flags);
|
||||
for (i = 0; i < len; i++)
|
||||
ltq_w8(buf[i], (void __iomem *)(nandaddr | NAND_WRITE_DATA));
|
||||
- spin_unlock_irqrestore(&ebu_lock, flags);
|
||||
}
|
||||
|
||||
static int xway_nand_probe(struct platform_device *pdev)
|
||||
@ -1,125 +0,0 @@ |
||||
From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 9 Sep 2014 23:12:15 +0200
|
||||
Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/mtd/nand/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 63 insertions(+)
|
||||
|
||||
--- a/drivers/mtd/nand/xway_nand.c
|
||||
+++ b/drivers/mtd/nand/xway_nand.c
|
||||
@@ -54,8 +54,27 @@
|
||||
#define NAND_CON_CSMUX (1 << 1)
|
||||
#define NAND_CON_NANDM 1
|
||||
|
||||
+#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr))
|
||||
+#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400)
|
||||
+#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080)
|
||||
+
|
||||
static u32 xway_latchcmd;
|
||||
|
||||
+/*
|
||||
+ * req_mask provides a mechanism to prevent interference between
|
||||
+ * nand and pci (probably only relevant for the BT Home Hub 2B).
|
||||
+ * Setting it causes the corresponding pci req pins to be masked
|
||||
+ * during nand access, and also moves ebu locking from the read/write
|
||||
+ * functions to the chip select function to ensure that the whole
|
||||
+ * operation runs with interrupts disabled.
|
||||
+ * In addition it switches on some extra waiting in xway_cmd_ctrl().
|
||||
+ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
|
||||
+ * which in turn seems to be necessary for the nor chip to be recognised
|
||||
+ * reliably, on a board (Home Hub 2B again) which has both nor and nand.
|
||||
+ */
|
||||
+
|
||||
+static __be32 req_mask = 0;
|
||||
+
|
||||
static void xway_reset_chip(struct nand_chip *chip)
|
||||
{
|
||||
unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
|
||||
@@ -86,12 +105,24 @@ static void xway_select_chip(struct mtd_
|
||||
case -1:
|
||||
ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
|
||||
ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
|
||||
+
|
||||
+ if (req_mask) {
|
||||
+ /* Unmask all external PCI request */
|
||||
+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
|
||||
+ }
|
||||
spin_unlock_irqrestore(&ebu_lock, csflags);
|
||||
+
|
||||
break;
|
||||
case 0:
|
||||
spin_lock_irqsave(&ebu_lock, csflags);
|
||||
+ if (req_mask) {
|
||||
+ /* Mask all external PCI request */
|
||||
+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
|
||||
+ }
|
||||
+
|
||||
ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
|
||||
ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
|
||||
+
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
@@ -103,6 +134,12 @@ static void xway_cmd_ctrl(struct mtd_inf
|
||||
struct nand_chip *this = mtd->priv;
|
||||
unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
|
||||
|
||||
+ if (req_mask) {
|
||||
+ if (cmd != NAND_CMD_STATUS)
|
||||
+ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */
|
||||
+ }
|
||||
+
|
||||
+
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
if (ctrl & NAND_CLE)
|
||||
xway_latchcmd = NAND_WRITE_CMD;
|
||||
@@ -115,6 +152,24 @@ static void xway_cmd_ctrl(struct mtd_inf
|
||||
while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
|
||||
;
|
||||
}
|
||||
+
|
||||
+ if (req_mask) {
|
||||
+ /*
|
||||
+ * program and erase have their own busy handlers
|
||||
+ * status and sequential in needs no delay
|
||||
+ */
|
||||
+ switch (cmd) {
|
||||
+ case NAND_CMD_ERASE1:
|
||||
+ case NAND_CMD_SEQIN:
|
||||
+ case NAND_CMD_STATUS:
|
||||
+ case NAND_CMD_READID:
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ /* wait until command is processed */
|
||||
+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
|
||||
+ ;
|
||||
+ }
|
||||
}
|
||||
|
||||
static int xway_dev_ready(struct mtd_info *mtd)
|
||||
@@ -157,6 +212,8 @@ static int xway_nand_probe(struct platfo
|
||||
{
|
||||
struct nand_chip *this = platform_get_drvdata(pdev);
|
||||
unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
|
||||
+ const __be32 *req_mask_ptr = of_get_property(pdev->dev.of_node,
|
||||
+ "req-mask", NULL);
|
||||
const __be32 *cs = of_get_property(pdev->dev.of_node,
|
||||
"lantiq,cs", NULL);
|
||||
u32 cs_flag = 0;
|
||||
@@ -165,6 +222,12 @@ static int xway_nand_probe(struct platfo
|
||||
if (cs && (*cs == 1))
|
||||
cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
|
||||
|
||||
+ /*
|
||||
+ * Load the PCI req lines to mask from the device tree. If the
|
||||
+ * property is not present, setting req_mask to 0 disables masking.
|
||||
+ */
|
||||
+ req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
|
||||
+
|
||||
/* setup the EBU to run in NAND mode on our base addr */
|
||||
ltq_ebu_w32(CPHYSADDR(nandaddr)
|
||||
| ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
|
||||
@ -1,25 +0,0 @@ |
||||
From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 7 Aug 2014 18:18:00 +0200
|
||||
Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/mtd/maps/lantiq-flash.c | 6 +++++-
|
||||
1 file changed, 5 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mtd/maps/lantiq-flash.c
|
||||
+++ b/drivers/mtd/maps/lantiq-flash.c
|
||||
@@ -138,7 +138,11 @@ ltq_mtd_probe(struct platform_device *pd
|
||||
if (!ltq_mtd->map)
|
||||
return -ENOMEM;
|
||||
|
||||
- ltq_mtd->map->phys = ltq_mtd->res->start;
|
||||
+ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
|
||||
+ ltq_mtd->map->phys = NO_XIP;
|
||||
+ else
|
||||
+ ltq_mtd->map->phys = ltq_mtd->res->start;
|
||||
+ ltq_mtd->res->start;
|
||||
ltq_mtd->map->size = resource_size(ltq_mtd->res);
|
||||
ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res);
|
||||
if (IS_ERR(ltq_mtd->map->virt))
|
||||
@ -1,44 +0,0 @@ |
||||
From 4400e1f593ea40a51912128adb4f53d59e62cad8 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 10 Sep 2014 22:40:18 +0200
|
||||
Subject: [PATCH 22/36] MTD: m25p80: allow loading mtd name from OF
|
||||
|
||||
In accordance with the physmap flash we should honour the linux,mtd-name
|
||||
property when deciding what name the mtd device has.
|
||||
|
||||
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/mtd/devices/m25p80.c | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
--- a/drivers/mtd/devices/m25p80.c
|
||||
+++ b/drivers/mtd/devices/m25p80.c
|
||||
@@ -19,6 +19,7 @@
|
||||
#include <linux/errno.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/device.h>
|
||||
+#include <linux/of.h>
|
||||
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
@@ -204,6 +205,10 @@ static int m25p_probe(struct spi_device
|
||||
enum read_mode mode = SPI_NOR_NORMAL;
|
||||
char *flash_name = NULL;
|
||||
int ret;
|
||||
+ const char __maybe_unused *of_mtd_name = NULL;
|
||||
+
|
||||
+ of_property_read_string(spi->dev.of_node,
|
||||
+ "linux,mtd-name", &of_mtd_name);
|
||||
|
||||
data = dev_get_platdata(&spi->dev);
|
||||
|
||||
@@ -234,6 +239,8 @@ static int m25p_probe(struct spi_device
|
||||
|
||||
if (data && data->name)
|
||||
nor->mtd.name = data->name;
|
||||
+ else if (of_mtd_name)
|
||||
+ nor->mtd.name = of_mtd_name;
|
||||
|
||||
/* For some (historical?) reason many platforms provide two different
|
||||
* names in flash_platform_data: "name" and "type". Quite often name is
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,53 +0,0 @@ |
||||
From c6feeeb407a3b8a6597ae377ba4dd138e185e3dd Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 27 Jul 2014 09:38:50 +0100
|
||||
Subject: [PATCH 26/36] NET: multi phy support
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/net/phy/phy.c | 9 ++++++---
|
||||
include/linux/phy.h | 1 +
|
||||
2 files changed, 7 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/net/phy/phy.c
|
||||
+++ b/drivers/net/phy/phy.c
|
||||
@@ -893,7 +893,8 @@ void phy_state_machine(struct work_struc
|
||||
/* If the link is down, give up on negotiation for now */
|
||||
if (!phydev->link) {
|
||||
phydev->state = PHY_NOLINK;
|
||||
- netif_carrier_off(phydev->attached_dev);
|
||||
+ if (!phydev->no_auto_carrier_off)
|
||||
+ netif_carrier_off(phydev->attached_dev);
|
||||
phydev->adjust_link(phydev->attached_dev);
|
||||
break;
|
||||
}
|
||||
@@ -985,7 +986,8 @@ void phy_state_machine(struct work_struc
|
||||
netif_carrier_on(phydev->attached_dev);
|
||||
} else {
|
||||
phydev->state = PHY_NOLINK;
|
||||
- netif_carrier_off(phydev->attached_dev);
|
||||
+ if (!phydev->no_auto_carrier_off)
|
||||
+ netif_carrier_off(phydev->attached_dev);
|
||||
}
|
||||
|
||||
phydev->adjust_link(phydev->attached_dev);
|
||||
@@ -997,7 +999,8 @@ void phy_state_machine(struct work_struc
|
||||
case PHY_HALTED:
|
||||
if (phydev->link) {
|
||||
phydev->link = 0;
|
||||
- netif_carrier_off(phydev->attached_dev);
|
||||
+ if (!phydev->no_auto_carrier_off)
|
||||
+ netif_carrier_off(phydev->attached_dev);
|
||||
phydev->adjust_link(phydev->attached_dev);
|
||||
do_suspend = true;
|
||||
}
|
||||
--- a/include/linux/phy.h
|
||||
+++ b/include/linux/phy.h
|
||||
@@ -377,6 +377,7 @@ struct phy_device {
|
||||
bool is_pseudo_fixed_link;
|
||||
bool has_fixups;
|
||||
bool suspended;
|
||||
+ bool no_auto_carrier_off;
|
||||
|
||||
enum phy_state state;
|
||||
|
||||
@ -1,911 +0,0 @@ |
||||
From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 9 Sep 2014 22:45:34 +0200
|
||||
Subject: [PATCH 28/36] NET: lantiq: various etop fixes
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++-----------
|
||||
1 file changed, 389 insertions(+), 166 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/lantiq_etop.c
|
||||
+++ b/drivers/net/ethernet/lantiq_etop.c
|
||||
@@ -11,7 +11,7 @@
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
|
||||
+ * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
@@ -30,11 +30,16 @@
|
||||
#include <linux/mm.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/ethtool.h>
|
||||
+#include <linux/if_vlan.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/module.h>
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/of_net.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/checksum.h>
|
||||
|
||||
@@ -42,7 +47,7 @@
|
||||
#include <xway_dma.h>
|
||||
#include <lantiq_platform.h>
|
||||
|
||||
-#define LTQ_ETOP_MDIO 0x11804
|
||||
+#define LTQ_ETOP_MDIO_ACC 0x11804
|
||||
#define MDIO_REQUEST 0x80000000
|
||||
#define MDIO_READ 0x40000000
|
||||
#define MDIO_ADDR_MASK 0x1f
|
||||
@@ -51,44 +56,91 @@
|
||||
#define MDIO_REG_OFFSET 0x10
|
||||
#define MDIO_VAL_MASK 0xffff
|
||||
|
||||
-#define PPE32_CGEN 0x800
|
||||
-#define LQ_PPE32_ENET_MAC_CFG 0x1840
|
||||
+#define LTQ_ETOP_MDIO_CFG 0x11800
|
||||
+#define MDIO_CFG_MASK 0x6
|
||||
+
|
||||
+#define LTQ_ETOP_CFG 0x11808
|
||||
+#define LTQ_ETOP_IGPLEN 0x11820
|
||||
+#define LTQ_ETOP_MAC_CFG 0x11840
|
||||
|
||||
#define LTQ_ETOP_ENETS0 0x11850
|
||||
#define LTQ_ETOP_MAC_DA0 0x1186C
|
||||
#define LTQ_ETOP_MAC_DA1 0x11870
|
||||
-#define LTQ_ETOP_CFG 0x16020
|
||||
-#define LTQ_ETOP_IGPLEN 0x16080
|
||||
+
|
||||
+#define MAC_CFG_MASK 0xfff
|
||||
+#define MAC_CFG_CGEN (1 << 11)
|
||||
+#define MAC_CFG_DUPLEX (1 << 2)
|
||||
+#define MAC_CFG_SPEED (1 << 1)
|
||||
+#define MAC_CFG_LINK (1 << 0)
|
||||
|
||||
#define MAX_DMA_CHAN 0x8
|
||||
#define MAX_DMA_CRC_LEN 0x4
|
||||
#define MAX_DMA_DATA_LEN 0x600
|
||||
|
||||
#define ETOP_FTCU BIT(28)
|
||||
-#define ETOP_MII_MASK 0xf
|
||||
-#define ETOP_MII_NORMAL 0xd
|
||||
-#define ETOP_MII_REVERSE 0xe
|
||||
#define ETOP_PLEN_UNDER 0x40
|
||||
-#define ETOP_CGEN 0x800
|
||||
+#define ETOP_CFG_MII0 0x01
|
||||
|
||||
-/* use 2 static channels for TX/RX */
|
||||
-#define LTQ_ETOP_TX_CHANNEL 1
|
||||
-#define LTQ_ETOP_RX_CHANNEL 6
|
||||
-#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
|
||||
-#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
|
||||
+#define ETOP_CFG_MASK 0xfff
|
||||
+#define ETOP_CFG_FEN0 (1 << 8)
|
||||
+#define ETOP_CFG_SEN0 (1 << 6)
|
||||
+#define ETOP_CFG_OFF1 (1 << 3)
|
||||
+#define ETOP_CFG_REMII0 (1 << 1)
|
||||
+#define ETOP_CFG_OFF0 (1 << 0)
|
||||
+
|
||||
+#define LTQ_GBIT_MDIO_CTL 0xCC
|
||||
+#define LTQ_GBIT_MDIO_DATA 0xd0
|
||||
+#define LTQ_GBIT_GCTL0 0x68
|
||||
+#define LTQ_GBIT_PMAC_HD_CTL 0x8c
|
||||
+#define LTQ_GBIT_P0_CTL 0x4
|
||||
+#define LTQ_GBIT_PMAC_RX_IPG 0xa8
|
||||
+#define LTQ_GBIT_RGMII_CTL 0x78
|
||||
+
|
||||
+#define PMAC_HD_CTL_AS (1 << 19)
|
||||
+#define PMAC_HD_CTL_RXSH (1 << 22)
|
||||
+
|
||||
+/* Switch Enable (0=disable, 1=enable) */
|
||||
+#define GCTL0_SE 0x80000000
|
||||
+/* Disable MDIO auto polling (0=disable, 1=enable) */
|
||||
+#define PX_CTL_DMDIO 0x00400000
|
||||
+
|
||||
+/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
|
||||
+#define MDC_CLOCK_MASK 0xff000000
|
||||
+#define MDC_CLOCK_OFFSET 24
|
||||
+
|
||||
+/* register information for the gbit's MDIO bus */
|
||||
+#define MDIO_XR9_REQUEST 0x00008000
|
||||
+#define MDIO_XR9_READ 0x00000800
|
||||
+#define MDIO_XR9_WRITE 0x00000400
|
||||
+#define MDIO_XR9_REG_MASK 0x1f
|
||||
+#define MDIO_XR9_ADDR_MASK 0x1f
|
||||
+#define MDIO_XR9_RD_MASK 0xffff
|
||||
+#define MDIO_XR9_REG_OFFSET 0
|
||||
+#define MDIO_XR9_ADDR_OFFSET 5
|
||||
+#define MDIO_XR9_WR_OFFSET 16
|
||||
|
||||
+#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
|
||||
+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
|
||||
+
|
||||
+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
|
||||
#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
|
||||
#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
|
||||
#define ltq_etop_w32_mask(x, y, z) \
|
||||
ltq_w32_mask(x, y, ltq_etop_membase + (z))
|
||||
|
||||
-#define DRV_VERSION "1.0"
|
||||
+#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
|
||||
+#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
|
||||
+#define ltq_gbit_w32_mask(x, y, z) \
|
||||
+ ltq_w32_mask(x, y, ltq_gbit_membase + (z))
|
||||
+
|
||||
+#define DRV_VERSION "1.2"
|
||||
|
||||
static void __iomem *ltq_etop_membase;
|
||||
+static void __iomem *ltq_gbit_membase;
|
||||
|
||||
struct ltq_etop_chan {
|
||||
- int idx;
|
||||
int tx_free;
|
||||
+ int irq;
|
||||
struct net_device *netdev;
|
||||
struct napi_struct napi;
|
||||
struct ltq_dma_channel dma;
|
||||
@@ -98,22 +150,35 @@ struct ltq_etop_chan {
|
||||
struct ltq_etop_priv {
|
||||
struct net_device *netdev;
|
||||
struct platform_device *pdev;
|
||||
- struct ltq_eth_data *pldata;
|
||||
struct resource *res;
|
||||
|
||||
struct mii_bus *mii_bus;
|
||||
struct phy_device *phydev;
|
||||
|
||||
- struct ltq_etop_chan ch[MAX_DMA_CHAN];
|
||||
- int tx_free[MAX_DMA_CHAN >> 1];
|
||||
+ struct ltq_etop_chan txch;
|
||||
+ struct ltq_etop_chan rxch;
|
||||
+
|
||||
+ int tx_irq;
|
||||
+ int rx_irq;
|
||||
+
|
||||
+ unsigned char mac[6];
|
||||
+ int mii_mode;
|
||||
|
||||
spinlock_t lock;
|
||||
+
|
||||
+ struct clk *clk_ppe;
|
||||
+ struct clk *clk_switch;
|
||||
+ struct clk *clk_ephy;
|
||||
+ struct clk *clk_ephycgu;
|
||||
};
|
||||
|
||||
+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
|
||||
+ int phy_reg, u16 phy_data);
|
||||
+
|
||||
static int
|
||||
ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
|
||||
{
|
||||
- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
|
||||
+ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
|
||||
if (!ch->skb[ch->dma.desc])
|
||||
return -ENOMEM;
|
||||
ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
|
||||
@@ -148,8 +213,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
skb_put(skb, len);
|
||||
+ skb->dev = ch->netdev;
|
||||
skb->protocol = eth_type_trans(skb, ch->netdev);
|
||||
netif_receive_skb(skb);
|
||||
+ ch->netdev->stats.rx_packets++;
|
||||
+ ch->netdev->stats.rx_bytes += len;
|
||||
}
|
||||
|
||||
static int
|
||||
@@ -157,8 +225,10 @@ ltq_etop_poll_rx(struct napi_struct *nap
|
||||
{
|
||||
struct ltq_etop_chan *ch = container_of(napi,
|
||||
struct ltq_etop_chan, napi);
|
||||
+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
|
||||
int rx = 0;
|
||||
int complete = 0;
|
||||
+ unsigned long flags;
|
||||
|
||||
while ((rx < budget) && !complete) {
|
||||
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
|
||||
@@ -172,7 +242,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
|
||||
}
|
||||
if (complete || !rx) {
|
||||
napi_complete(&ch->napi);
|
||||
+ spin_lock_irqsave(&priv->lock, flags);
|
||||
ltq_dma_ack_irq(&ch->dma);
|
||||
+ spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
return rx;
|
||||
}
|
||||
@@ -184,12 +256,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
|
||||
container_of(napi, struct ltq_etop_chan, napi);
|
||||
struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
|
||||
struct netdev_queue *txq =
|
||||
- netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
|
||||
+ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
while ((ch->dma.desc_base[ch->tx_free].ctl &
|
||||
(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
|
||||
+ ch->netdev->stats.tx_packets++;
|
||||
+ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
|
||||
dev_kfree_skb_any(ch->skb[ch->tx_free]);
|
||||
ch->skb[ch->tx_free] = NULL;
|
||||
memset(&ch->dma.desc_base[ch->tx_free], 0,
|
||||
@@ -202,7 +276,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
|
||||
if (netif_tx_queue_stopped(txq))
|
||||
netif_tx_start_queue(txq);
|
||||
napi_complete(&ch->napi);
|
||||
+ spin_lock_irqsave(&priv->lock, flags);
|
||||
ltq_dma_ack_irq(&ch->dma);
|
||||
+ spin_unlock_irqrestore(&priv->lock, flags);
|
||||
return 1;
|
||||
}
|
||||
|
||||
@@ -210,9 +286,10 @@ static irqreturn_t
|
||||
ltq_etop_dma_irq(int irq, void *_priv)
|
||||
{
|
||||
struct ltq_etop_priv *priv = _priv;
|
||||
- int ch = irq - LTQ_DMA_CH0_INT;
|
||||
-
|
||||
- napi_schedule(&priv->ch[ch].napi);
|
||||
+ if (irq == priv->txch.dma.irq)
|
||||
+ napi_schedule(&priv->txch.napi);
|
||||
+ else
|
||||
+ napi_schedule(&priv->rxch.napi);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
@@ -224,7 +301,7 @@ ltq_etop_free_channel(struct net_device
|
||||
ltq_dma_free(&ch->dma);
|
||||
if (ch->dma.irq)
|
||||
free_irq(ch->dma.irq, priv);
|
||||
- if (IS_RX(ch->idx)) {
|
||||
+ if (ch == &priv->txch) {
|
||||
int desc;
|
||||
for (desc = 0; desc < LTQ_DESC_NUM; desc++)
|
||||
dev_kfree_skb_any(ch->skb[ch->dma.desc]);
|
||||
@@ -235,65 +312,133 @@ static void
|
||||
ltq_etop_hw_exit(struct net_device *dev)
|
||||
{
|
||||
struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
- int i;
|
||||
|
||||
- ltq_pmu_disable(PMU_PPE);
|
||||
- for (i = 0; i < MAX_DMA_CHAN; i++)
|
||||
- if (IS_TX(i) || IS_RX(i))
|
||||
- ltq_etop_free_channel(dev, &priv->ch[i]);
|
||||
+ clk_disable(priv->clk_ppe);
|
||||
+
|
||||
+ if (of_machine_is_compatible("lantiq,ar9"))
|
||||
+ clk_disable(priv->clk_switch);
|
||||
+
|
||||
+ if (of_machine_is_compatible("lantiq,ase")) {
|
||||
+ clk_disable(priv->clk_ephy);
|
||||
+ clk_disable(priv->clk_ephycgu);
|
||||
+ }
|
||||
+
|
||||
+ ltq_etop_free_channel(dev, &priv->txch);
|
||||
+ ltq_etop_free_channel(dev, &priv->rxch);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+ltq_etop_gbit_init(struct net_device *dev)
|
||||
+{
|
||||
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
+
|
||||
+ clk_enable(priv->clk_switch);
|
||||
+
|
||||
+ /* enable gbit port0 on the SoC */
|
||||
+ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
|
||||
+
|
||||
+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
|
||||
+ /* disable MDIO auto polling mode */
|
||||
+ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
|
||||
+ /* set 1522 packet size */
|
||||
+ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
|
||||
+ /* disable pmac & dmac headers */
|
||||
+ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
|
||||
+ LTQ_GBIT_PMAC_HD_CTL);
|
||||
+ /* Due to traffic halt when burst length 8,
|
||||
+ replace default IPG value with 0x3B */
|
||||
+ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
|
||||
+ /* set mdc clock to 2.5 MHz */
|
||||
+ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
|
||||
+ LTQ_GBIT_RGMII_CTL);
|
||||
}
|
||||
|
||||
static int
|
||||
ltq_etop_hw_init(struct net_device *dev)
|
||||
{
|
||||
struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
- int i;
|
||||
+ int mii_mode = priv->mii_mode;
|
||||
|
||||
- ltq_pmu_enable(PMU_PPE);
|
||||
+ clk_enable(priv->clk_ppe);
|
||||
+
|
||||
+ if (of_machine_is_compatible("lantiq,ar9")) {
|
||||
+ ltq_etop_gbit_init(dev);
|
||||
+ /* force the etops link to the gbit to MII */
|
||||
+ mii_mode = PHY_INTERFACE_MODE_MII;
|
||||
+ }
|
||||
+ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
|
||||
+ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
|
||||
+ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
|
||||
|
||||
- switch (priv->pldata->mii_mode) {
|
||||
+ switch (mii_mode) {
|
||||
case PHY_INTERFACE_MODE_RMII:
|
||||
- ltq_etop_w32_mask(ETOP_MII_MASK,
|
||||
- ETOP_MII_REVERSE, LTQ_ETOP_CFG);
|
||||
+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
|
||||
+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
|
||||
break;
|
||||
|
||||
case PHY_INTERFACE_MODE_MII:
|
||||
- ltq_etop_w32_mask(ETOP_MII_MASK,
|
||||
- ETOP_MII_NORMAL, LTQ_ETOP_CFG);
|
||||
+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
|
||||
+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
|
||||
break;
|
||||
|
||||
default:
|
||||
+ if (of_machine_is_compatible("lantiq,ase")) {
|
||||
+ clk_enable(priv->clk_ephy);
|
||||
+ /* disable external MII */
|
||||
+ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
|
||||
+ /* enable clock for internal PHY */
|
||||
+ clk_enable(priv->clk_ephycgu);
|
||||
+ /* we need to write this magic to the internal phy to
|
||||
+ make it work */
|
||||
+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
|
||||
+ pr_info("Selected EPHY mode\n");
|
||||
+ break;
|
||||
+ }
|
||||
netdev_err(dev, "unknown mii mode %d\n",
|
||||
- priv->pldata->mii_mode);
|
||||
+ mii_mode);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
- /* enable crc generation */
|
||||
- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+ltq_etop_dma_init(struct net_device *dev)
|
||||
+{
|
||||
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
+ int tx = priv->tx_irq - LTQ_DMA_ETOP;
|
||||
+ int rx = priv->rx_irq - LTQ_DMA_ETOP;
|
||||
+ int err;
|
||||
|
||||
ltq_dma_init_port(DMA_PORT_ETOP);
|
||||
|
||||
- for (i = 0; i < MAX_DMA_CHAN; i++) {
|
||||
- int irq = LTQ_DMA_CH0_INT + i;
|
||||
- struct ltq_etop_chan *ch = &priv->ch[i];
|
||||
-
|
||||
- ch->idx = ch->dma.nr = i;
|
||||
-
|
||||
- if (IS_TX(i)) {
|
||||
- ltq_dma_alloc_tx(&ch->dma);
|
||||
- request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
|
||||
- } else if (IS_RX(i)) {
|
||||
- ltq_dma_alloc_rx(&ch->dma);
|
||||
- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
|
||||
- ch->dma.desc++)
|
||||
- if (ltq_etop_alloc_skb(ch))
|
||||
- return -ENOMEM;
|
||||
- ch->dma.desc = 0;
|
||||
- request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
|
||||
+ priv->txch.dma.nr = tx;
|
||||
+ ltq_dma_alloc_tx(&priv->txch.dma);
|
||||
+ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
|
||||
+ if (err) {
|
||||
+ netdev_err(dev, "failed to allocate tx irq\n");
|
||||
+ goto err_out;
|
||||
+ }
|
||||
+ priv->txch.dma.irq = priv->tx_irq;
|
||||
+
|
||||
+ priv->rxch.dma.nr = rx;
|
||||
+ ltq_dma_alloc_rx(&priv->rxch.dma);
|
||||
+ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
|
||||
+ priv->rxch.dma.desc++) {
|
||||
+ if (ltq_etop_alloc_skb(&priv->rxch)) {
|
||||
+ netdev_err(dev, "failed to allocate skbs\n");
|
||||
+ err = -ENOMEM;
|
||||
+ goto err_out;
|
||||
}
|
||||
- ch->dma.irq = irq;
|
||||
}
|
||||
- return 0;
|
||||
+ priv->rxch.dma.desc = 0;
|
||||
+ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
|
||||
+ if (err)
|
||||
+ netdev_err(dev, "failed to allocate rx irq\n");
|
||||
+ else
|
||||
+ priv->rxch.dma.irq = priv->rx_irq;
|
||||
+err_out:
|
||||
+ return err;
|
||||
}
|
||||
|
||||
static void
|
||||
@@ -309,7 +454,10 @@ ltq_etop_get_settings(struct net_device
|
||||
{
|
||||
struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
|
||||
- return phy_ethtool_gset(priv->phydev, cmd);
|
||||
+ if (priv->phydev)
|
||||
+ return phy_ethtool_gset(priv->phydev, cmd);
|
||||
+ else
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
@@ -317,7 +465,10 @@ ltq_etop_set_settings(struct net_device
|
||||
{
|
||||
struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
|
||||
- return phy_ethtool_sset(priv->phydev, cmd);
|
||||
+ if (priv->phydev)
|
||||
+ return phy_ethtool_sset(priv->phydev, cmd);
|
||||
+ else
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
@@ -325,7 +476,10 @@ ltq_etop_nway_reset(struct net_device *d
|
||||
{
|
||||
struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
|
||||
- return phy_start_aneg(priv->phydev);
|
||||
+ if (priv->phydev)
|
||||
+ return phy_start_aneg(priv->phydev);
|
||||
+ else
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static const struct ethtool_ops ltq_etop_ethtool_ops = {
|
||||
@@ -336,6 +490,39 @@ static const struct ethtool_ops ltq_etop
|
||||
};
|
||||
|
||||
static int
|
||||
+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
|
||||
+ int phy_reg, u16 phy_data)
|
||||
+{
|
||||
+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
|
||||
+ (phy_data << MDIO_XR9_WR_OFFSET) |
|
||||
+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
|
||||
+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
|
||||
+
|
||||
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
|
||||
+ ;
|
||||
+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
|
||||
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
|
||||
+ ;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
|
||||
+{
|
||||
+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
|
||||
+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
|
||||
+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
|
||||
+
|
||||
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
|
||||
+ ;
|
||||
+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
|
||||
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
|
||||
+ ;
|
||||
+ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
|
||||
+ return val;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
|
||||
{
|
||||
u32 val = MDIO_REQUEST |
|
||||
@@ -343,9 +530,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
|
||||
((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
|
||||
phy_data;
|
||||
|
||||
- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
|
||||
+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
|
||||
;
|
||||
- ltq_etop_w32(val, LTQ_ETOP_MDIO);
|
||||
+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -356,12 +543,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
|
||||
((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
|
||||
((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
|
||||
|
||||
- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
|
||||
+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
|
||||
;
|
||||
- ltq_etop_w32(val, LTQ_ETOP_MDIO);
|
||||
- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
|
||||
+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
|
||||
+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
|
||||
;
|
||||
- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
|
||||
+ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
|
||||
return val;
|
||||
}
|
||||
|
||||
@@ -376,14 +563,18 @@ ltq_etop_mdio_probe(struct net_device *d
|
||||
{
|
||||
struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
struct phy_device *phydev = NULL;
|
||||
- int phy_addr;
|
||||
+ u32 phy_supported = (SUPPORTED_10baseT_Half
|
||||
+ | SUPPORTED_10baseT_Full
|
||||
+ | SUPPORTED_100baseT_Half
|
||||
+ | SUPPORTED_100baseT_Full
|
||||
+ | SUPPORTED_Autoneg
|
||||
+ | SUPPORTED_MII
|
||||
+ | SUPPORTED_TP);
|
||||
|
||||
- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
|
||||
- if (priv->mii_bus->phy_map[phy_addr]) {
|
||||
- phydev = priv->mii_bus->phy_map[phy_addr];
|
||||
- break;
|
||||
- }
|
||||
- }
|
||||
+ if (of_machine_is_compatible("lantiq,ase"))
|
||||
+ phydev = priv->mii_bus->phy_map[8];
|
||||
+ else
|
||||
+ phydev = priv->mii_bus->phy_map[0];
|
||||
|
||||
if (!phydev) {
|
||||
netdev_err(dev, "no PHY found\n");
|
||||
@@ -391,21 +582,18 @@ ltq_etop_mdio_probe(struct net_device *d
|
||||
}
|
||||
|
||||
phydev = phy_connect(dev, dev_name(&phydev->dev),
|
||||
- <q_etop_mdio_link, priv->pldata->mii_mode);
|
||||
+ <q_etop_mdio_link, priv->mii_mode);
|
||||
|
||||
if (IS_ERR(phydev)) {
|
||||
netdev_err(dev, "Could not attach to PHY\n");
|
||||
return PTR_ERR(phydev);
|
||||
}
|
||||
|
||||
- phydev->supported &= (SUPPORTED_10baseT_Half
|
||||
- | SUPPORTED_10baseT_Full
|
||||
- | SUPPORTED_100baseT_Half
|
||||
- | SUPPORTED_100baseT_Full
|
||||
- | SUPPORTED_Autoneg
|
||||
- | SUPPORTED_MII
|
||||
- | SUPPORTED_TP);
|
||||
+ if (of_machine_is_compatible("lantiq,ar9"))
|
||||
+ phy_supported |= SUPPORTED_1000baseT_Half
|
||||
+ | SUPPORTED_1000baseT_Full;
|
||||
|
||||
+ phydev->supported &= phy_supported;
|
||||
phydev->advertising = phydev->supported;
|
||||
priv->phydev = phydev;
|
||||
pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
|
||||
@@ -430,8 +618,13 @@ ltq_etop_mdio_init(struct net_device *de
|
||||
}
|
||||
|
||||
priv->mii_bus->priv = dev;
|
||||
- priv->mii_bus->read = ltq_etop_mdio_rd;
|
||||
- priv->mii_bus->write = ltq_etop_mdio_wr;
|
||||
+ if (of_machine_is_compatible("lantiq,ar9")) {
|
||||
+ priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
|
||||
+ priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
|
||||
+ } else {
|
||||
+ priv->mii_bus->read = ltq_etop_mdio_rd;
|
||||
+ priv->mii_bus->write = ltq_etop_mdio_wr;
|
||||
+ }
|
||||
priv->mii_bus->name = "ltq_mii";
|
||||
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
|
||||
priv->pdev->name, priv->pdev->id);
|
||||
@@ -480,17 +673,19 @@ static int
|
||||
ltq_etop_open(struct net_device *dev)
|
||||
{
|
||||
struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
- int i;
|
||||
+ unsigned long flags;
|
||||
|
||||
- for (i = 0; i < MAX_DMA_CHAN; i++) {
|
||||
- struct ltq_etop_chan *ch = &priv->ch[i];
|
||||
+ napi_enable(&priv->txch.napi);
|
||||
+ napi_enable(&priv->rxch.napi);
|
||||
+
|
||||
+ spin_lock_irqsave(&priv->lock, flags);
|
||||
+ ltq_dma_open(&priv->txch.dma);
|
||||
+ ltq_dma_open(&priv->rxch.dma);
|
||||
+ spin_unlock_irqrestore(&priv->lock, flags);
|
||||
+
|
||||
+ if (priv->phydev)
|
||||
+ phy_start(priv->phydev);
|
||||
|
||||
- if (!IS_TX(i) && (!IS_RX(i)))
|
||||
- continue;
|
||||
- ltq_dma_open(&ch->dma);
|
||||
- napi_enable(&ch->napi);
|
||||
- }
|
||||
- phy_start(priv->phydev);
|
||||
netif_tx_start_all_queues(dev);
|
||||
return 0;
|
||||
}
|
||||
@@ -499,18 +694,19 @@ static int
|
||||
ltq_etop_stop(struct net_device *dev)
|
||||
{
|
||||
struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
- int i;
|
||||
+ unsigned long flags;
|
||||
|
||||
netif_tx_stop_all_queues(dev);
|
||||
- phy_stop(priv->phydev);
|
||||
- for (i = 0; i < MAX_DMA_CHAN; i++) {
|
||||
- struct ltq_etop_chan *ch = &priv->ch[i];
|
||||
-
|
||||
- if (!IS_RX(i) && !IS_TX(i))
|
||||
- continue;
|
||||
- napi_disable(&ch->napi);
|
||||
- ltq_dma_close(&ch->dma);
|
||||
- }
|
||||
+ if (priv->phydev)
|
||||
+ phy_stop(priv->phydev);
|
||||
+ napi_disable(&priv->txch.napi);
|
||||
+ napi_disable(&priv->rxch.napi);
|
||||
+
|
||||
+ spin_lock_irqsave(&priv->lock, flags);
|
||||
+ ltq_dma_close(&priv->txch.dma);
|
||||
+ ltq_dma_close(&priv->rxch.dma);
|
||||
+ spin_unlock_irqrestore(&priv->lock, flags);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -520,16 +716,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
|
||||
int queue = skb_get_queue_mapping(skb);
|
||||
struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
|
||||
struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
|
||||
- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
|
||||
- int len;
|
||||
+ struct ltq_dma_desc *desc =
|
||||
+ &priv->txch.dma.desc_base[priv->txch.dma.desc];
|
||||
unsigned long flags;
|
||||
u32 byte_offset;
|
||||
+ int len;
|
||||
|
||||
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
|
||||
|
||||
- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
|
||||
- dev_kfree_skb_any(skb);
|
||||
+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
|
||||
+ priv->txch.skb[priv->txch.dma.desc]) {
|
||||
netdev_err(dev, "tx ring full\n");
|
||||
netif_tx_stop_queue(txq);
|
||||
return NETDEV_TX_BUSY;
|
||||
@@ -537,7 +733,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
|
||||
|
||||
/* dma needs to start on a 16 byte aligned address */
|
||||
byte_offset = CPHYSADDR(skb->data) % 16;
|
||||
- ch->skb[ch->dma.desc] = skb;
|
||||
+ priv->txch.skb[priv->txch.dma.desc] = skb;
|
||||
|
||||
dev->trans_start = jiffies;
|
||||
|
||||
@@ -547,11 +743,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
|
||||
wmb();
|
||||
desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
|
||||
LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
|
||||
- ch->dma.desc++;
|
||||
- ch->dma.desc %= LTQ_DESC_NUM;
|
||||
+ priv->txch.dma.desc++;
|
||||
+ priv->txch.dma.desc %= LTQ_DESC_NUM;
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
|
||||
+ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
|
||||
netif_tx_stop_queue(txq);
|
||||
|
||||
return NETDEV_TX_OK;
|
||||
@@ -566,8 +762,10 @@ ltq_etop_change_mtu(struct net_device *d
|
||||
struct ltq_etop_priv *priv = netdev_priv(dev);
|
||||
unsigned long flags;
|
||||
|
||||
+ int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
|
||||
+
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
|
||||
+ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max,
|
||||
LTQ_ETOP_IGPLEN);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
@@ -638,6 +836,9 @@ ltq_etop_init(struct net_device *dev)
|
||||
if (err)
|
||||
goto err_hw;
|
||||
ltq_etop_change_mtu(dev, 1500);
|
||||
+ err = ltq_etop_dma_init(dev);
|
||||
+ if (err)
|
||||
+ goto err_hw;
|
||||
|
||||
memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
|
||||
if (!is_valid_ether_addr(mac.sa_data)) {
|
||||
@@ -655,9 +856,10 @@ ltq_etop_init(struct net_device *dev)
|
||||
dev->addr_assign_type = NET_ADDR_RANDOM;
|
||||
|
||||
ltq_etop_set_multicast_list(dev);
|
||||
- err = ltq_etop_mdio_init(dev);
|
||||
- if (err)
|
||||
- goto err_netdev;
|
||||
+ if (!ltq_etop_mdio_init(dev))
|
||||
+ dev->ethtool_ops = <q_etop_ethtool_ops;
|
||||
+ else
|
||||
+ pr_warn("etop: mdio probe failed\n");;
|
||||
return 0;
|
||||
|
||||
err_netdev:
|
||||
@@ -677,6 +879,9 @@ ltq_etop_tx_timeout(struct net_device *d
|
||||
err = ltq_etop_hw_init(dev);
|
||||
if (err)
|
||||
goto err_hw;
|
||||
+ err = ltq_etop_dma_init(dev);
|
||||
+ if (err)
|
||||
+ goto err_hw;
|
||||
dev->trans_start = jiffies;
|
||||
netif_wake_queue(dev);
|
||||
return;
|
||||
@@ -700,14 +905,19 @@ static const struct net_device_ops ltq_e
|
||||
.ndo_tx_timeout = ltq_etop_tx_timeout,
|
||||
};
|
||||
|
||||
-static int __init
|
||||
-ltq_etop_probe(struct platform_device *pdev)
|
||||
+static int ltq_etop_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct net_device *dev;
|
||||
struct ltq_etop_priv *priv;
|
||||
- struct resource *res;
|
||||
+ struct resource *res, *gbit_res, irqres[2];
|
||||
+ const u8 *mac;
|
||||
int err;
|
||||
- int i;
|
||||
+
|
||||
+ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
|
||||
+ if (err != 2) {
|
||||
+ dev_err(&pdev->dev, "failed to get etop irqs\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
@@ -733,30 +943,61 @@ ltq_etop_probe(struct platform_device *p
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
|
||||
- if (!dev) {
|
||||
- err = -ENOMEM;
|
||||
- goto err_out;
|
||||
+ if (of_machine_is_compatible("lantiq,ar9")) {
|
||||
+ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
+ if (!gbit_res) {
|
||||
+ dev_err(&pdev->dev, "failed to get gbit resource\n");
|
||||
+ err = -ENOENT;
|
||||
+ goto err_out;
|
||||
+ }
|
||||
+ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
|
||||
+ gbit_res->start, resource_size(gbit_res));
|
||||
+ if (!ltq_gbit_membase) {
|
||||
+ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
|
||||
+ pdev->id);
|
||||
+ err = -ENOMEM;
|
||||
+ goto err_out;
|
||||
+ }
|
||||
}
|
||||
+
|
||||
+ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
|
||||
strcpy(dev->name, "eth%d");
|
||||
dev->netdev_ops = <q_eth_netdev_ops;
|
||||
- dev->ethtool_ops = <q_etop_ethtool_ops;
|
||||
priv = netdev_priv(dev);
|
||||
priv->res = res;
|
||||
priv->pdev = pdev;
|
||||
- priv->pldata = dev_get_platdata(&pdev->dev);
|
||||
priv->netdev = dev;
|
||||
+ priv->tx_irq = irqres[0].start;
|
||||
+ priv->rx_irq = irqres[1].start;
|
||||
+ priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
|
||||
+
|
||||
+ mac = of_get_mac_address(pdev->dev.of_node);
|
||||
+ if (mac)
|
||||
+ memcpy(priv->mac, mac, ETH_ALEN);
|
||||
+
|
||||
+ priv->clk_ppe = clk_get(&pdev->dev, NULL);
|
||||
+ if (IS_ERR(priv->clk_ppe))
|
||||
+ return PTR_ERR(priv->clk_ppe);
|
||||
+ if (of_machine_is_compatible("lantiq,ar9")) {
|
||||
+ priv->clk_switch = clk_get(&pdev->dev, "switch");
|
||||
+ if (IS_ERR(priv->clk_switch))
|
||||
+ return PTR_ERR(priv->clk_switch);
|
||||
+ }
|
||||
+ if (of_machine_is_compatible("lantiq,ase")) {
|
||||
+ priv->clk_ephy = clk_get(&pdev->dev, "ephy");
|
||||
+ if (IS_ERR(priv->clk_ephy))
|
||||
+ return PTR_ERR(priv->clk_ephy);
|
||||
+ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
|
||||
+ if (IS_ERR(priv->clk_ephycgu))
|
||||
+ return PTR_ERR(priv->clk_ephycgu);
|
||||
+ }
|
||||
+
|
||||
spin_lock_init(&priv->lock);
|
||||
|
||||
- for (i = 0; i < MAX_DMA_CHAN; i++) {
|
||||
- if (IS_TX(i))
|
||||
- netif_napi_add(dev, &priv->ch[i].napi,
|
||||
- ltq_etop_poll_tx, 8);
|
||||
- else if (IS_RX(i))
|
||||
- netif_napi_add(dev, &priv->ch[i].napi,
|
||||
- ltq_etop_poll_rx, 32);
|
||||
- priv->ch[i].netdev = dev;
|
||||
- }
|
||||
+ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
|
||||
+ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
|
||||
+ priv->txch.netdev = dev;
|
||||
+ priv->rxch.netdev = dev;
|
||||
|
||||
err = register_netdev(dev);
|
||||
if (err)
|
||||
@@ -785,31 +1026,22 @@ ltq_etop_remove(struct platform_device *
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static const struct of_device_id ltq_etop_match[] = {
|
||||
+ { .compatible = "lantiq,etop-xway" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, ltq_etop_match);
|
||||
+
|
||||
static struct platform_driver ltq_mii_driver = {
|
||||
+ .probe = ltq_etop_probe,
|
||||
.remove = ltq_etop_remove,
|
||||
.driver = {
|
||||
.name = "ltq_etop",
|
||||
+ .of_match_table = ltq_etop_match,
|
||||
},
|
||||
};
|
||||
|
||||
-int __init
|
||||
-init_ltq_etop(void)
|
||||
-{
|
||||
- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe);
|
||||
-
|
||||
- if (ret)
|
||||
- pr_err("ltq_etop: Error registering platform driver!");
|
||||
- return ret;
|
||||
-}
|
||||
-
|
||||
-static void __exit
|
||||
-exit_ltq_etop(void)
|
||||
-{
|
||||
- platform_driver_unregister(<q_mii_driver);
|
||||
-}
|
||||
-
|
||||
-module_init(init_ltq_etop);
|
||||
-module_exit(exit_ltq_etop);
|
||||
+module_platform_driver(ltq_mii_driver);
|
||||
|
||||
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
|
||||
MODULE_DESCRIPTION("Lantiq SoC ETOP");
|
||||
@ -1,170 +0,0 @@ |
||||
From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 12 Aug 2014 20:49:27 +0200
|
||||
Subject: [PATCH 30/36] GPIO: add named gpio exports
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++
|
||||
drivers/gpio/gpiolib.c | 11 +++++--
|
||||
include/asm-generic/gpio.h | 5 +++
|
||||
include/linux/gpio/consumer.h | 8 +++++
|
||||
4 files changed, 90 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/gpio/gpiolib-of.c
|
||||
+++ b/drivers/gpio/gpiolib-of.c
|
||||
@@ -23,6 +23,8 @@
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/gpio/machine.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/platform_device.h>
|
||||
|
||||
#include "gpiolib.h"
|
||||
|
||||
@@ -450,3 +452,73 @@ void of_gpiochip_remove(struct gpio_chip
|
||||
gpiochip_remove_pin_ranges(chip);
|
||||
of_node_put(chip->of_node);
|
||||
}
|
||||
+
|
||||
+#ifdef CONFIG_GPIO_SYSFS
|
||||
+
|
||||
+static struct of_device_id gpio_export_ids[] = {
|
||||
+ { .compatible = "gpio-export" },
|
||||
+ { /* sentinel */ }
|
||||
+};
|
||||
+
|
||||
+static int __init of_gpio_export_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ struct device_node *cnp;
|
||||
+ u32 val;
|
||||
+ int nb = 0;
|
||||
+
|
||||
+ for_each_child_of_node(np, cnp) {
|
||||
+ const char *name = NULL;
|
||||
+ int gpio;
|
||||
+ bool dmc;
|
||||
+ int max_gpio = 1;
|
||||
+ int i;
|
||||
+
|
||||
+ of_property_read_string(cnp, "gpio-export,name", &name);
|
||||
+
|
||||
+ if (!name)
|
||||
+ max_gpio = of_gpio_count(cnp);
|
||||
+
|
||||
+ for (i = 0; i < max_gpio; i++) {
|
||||
+ unsigned flags = 0;
|
||||
+ enum of_gpio_flags of_flags;
|
||||
+
|
||||
+ gpio = of_get_gpio_flags(cnp, i, &of_flags);
|
||||
+
|
||||
+ if (of_flags == OF_GPIO_ACTIVE_LOW)
|
||||
+ flags |= GPIOF_ACTIVE_LOW;
|
||||
+
|
||||
+ if (!of_property_read_u32(cnp, "gpio-export,output", &val))
|
||||
+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
|
||||
+ else
|
||||
+ flags |= GPIOF_IN;
|
||||
+
|
||||
+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
|
||||
+ continue;
|
||||
+
|
||||
+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
|
||||
+ gpio_export_with_name(gpio, dmc, name);
|
||||
+ nb++;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver gpio_export_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "gpio-export",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = of_match_ptr(gpio_export_ids),
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init of_gpio_export_init(void)
|
||||
+{
|
||||
+ return platform_driver_probe(&gpio_export_driver, of_gpio_export_probe);
|
||||
+}
|
||||
+device_initcall(of_gpio_export_init);
|
||||
+
|
||||
+#endif
|
||||
--- a/include/asm-generic/gpio.h
|
||||
+++ b/include/asm-generic/gpio.h
|
||||
@@ -122,6 +122,12 @@ static inline int gpio_export(unsigned g
|
||||
return gpiod_export(gpio_to_desc(gpio), direction_may_change);
|
||||
}
|
||||
|
||||
+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
|
||||
+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
|
||||
+{
|
||||
+ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
|
||||
+}
|
||||
+
|
||||
static inline int gpio_export_link(struct device *dev, const char *name,
|
||||
unsigned gpio)
|
||||
{
|
||||
--- a/include/linux/gpio/consumer.h
|
||||
+++ b/include/linux/gpio/consumer.h
|
||||
@@ -427,6 +427,7 @@ static inline struct gpio_desc *devm_get
|
||||
|
||||
#if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
|
||||
|
||||
+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
|
||||
int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
|
||||
int gpiod_export_link(struct device *dev, const char *name,
|
||||
struct gpio_desc *desc);
|
||||
@@ -434,6 +435,13 @@ void gpiod_unexport(struct gpio_desc *de
|
||||
|
||||
#else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
|
||||
|
||||
+static inline int _gpiod_export(struct gpio_desc *desc,
|
||||
+ bool direction_may_change,
|
||||
+ const char *name)
|
||||
+{
|
||||
+ return -ENOSYS;
|
||||
+}
|
||||
+
|
||||
static inline int gpiod_export(struct gpio_desc *desc,
|
||||
bool direction_may_change)
|
||||
{
|
||||
--- a/drivers/gpio/gpiolib-sysfs.c
|
||||
+++ b/drivers/gpio/gpiolib-sysfs.c
|
||||
@@ -544,7 +544,7 @@ static struct class gpio_class = {
|
||||
*
|
||||
* Returns zero on success, else an error.
|
||||
*/
|
||||
-int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
|
||||
+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
|
||||
{
|
||||
struct gpio_chip *chip;
|
||||
struct gpiod_data *data;
|
||||
@@ -604,6 +604,8 @@ int gpiod_export(struct gpio_desc *desc,
|
||||
offset = gpio_chip_hwgpio(desc);
|
||||
if (chip->names && chip->names[offset])
|
||||
ioname = chip->names[offset];
|
||||
+ if (name)
|
||||
+ ioname = name;
|
||||
|
||||
dev = device_create_with_groups(&gpio_class, chip->dev,
|
||||
MKDEV(0, 0), data, gpio_groups,
|
||||
@@ -625,6 +627,12 @@ err_unlock:
|
||||
gpiod_dbg(desc, "%s: status %d\n", __func__, status);
|
||||
return status;
|
||||
}
|
||||
+EXPORT_SYMBOL_GPL(__gpiod_export);
|
||||
+
|
||||
+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
|
||||
+{
|
||||
+ return __gpiod_export(desc, direction_may_change, NULL);
|
||||
+}
|
||||
EXPORT_SYMBOL_GPL(gpiod_export);
|
||||
|
||||
static int match_export(struct device *dev, const void *desc)
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,219 +0,0 @@ |
||||
From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 10 Sep 2014 22:42:14 +0200
|
||||
Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +
|
||||
arch/mips/lantiq/xway/Makefile | 3 +
|
||||
arch/mips/lantiq/xway/ath5k_eep.c | 136 +++++++++++++++++++++
|
||||
arch/mips/lantiq/xway/eth_mac.c | 25 ++++
|
||||
drivers/net/ethernet/lantiq_etop.c | 6 +-
|
||||
5 files changed, 172 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c
|
||||
create mode 100644 arch/mips/lantiq/xway/eth_mac.c
|
||||
|
||||
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
|
||||
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
|
||||
@@ -104,5 +104,8 @@ int xrx200_gphy_boot(struct device *dev,
|
||||
extern void ltq_pmu_enable(unsigned int module);
|
||||
extern void ltq_pmu_disable(unsigned int module);
|
||||
|
||||
+/* allow the ethernet driver to load a flash mapped mac addr */
|
||||
+const u8* ltq_get_eth_mac(void);
|
||||
+
|
||||
#endif /* CONFIG_SOC_TYPE_XWAY */
|
||||
#endif /* _LTQ_XWAY_H__ */
|
||||
--- a/arch/mips/lantiq/xway/Makefile
|
||||
+++ b/arch/mips/lantiq/xway/Makefile
|
||||
@@ -8,4 +8,7 @@ endif
|
||||
|
||||
obj-y += vmmc.o
|
||||
|
||||
+obj-y += eth_mac.o
|
||||
+obj-$(CONFIG_PCI) += ath5k_eep.o
|
||||
+
|
||||
obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/lantiq/xway/ath5k_eep.c
|
||||
@@ -0,0 +1,136 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
|
||||
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
|
||||
+ * Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
|
||||
+ * Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
+ * Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
|
||||
+ * Copyright (C) 2015 Vittorio Gambaletta <openwrt@vittgam.net>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/etherdevice.h>
|
||||
+#include <linux/ath5k_platform.h>
|
||||
+#include <linux/pci.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/mtd/mtd.h>
|
||||
+#include <lantiq_soc.h>
|
||||
+
|
||||
+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
|
||||
+struct ath5k_platform_data ath5k_pdata;
|
||||
+static u8 athxk_eeprom_mac[6];
|
||||
+
|
||||
+static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
|
||||
+{
|
||||
+ dev->dev.platform_data = &ath5k_pdata;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ath5k_eep_load;
|
||||
+int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *mtd_np = NULL;
|
||||
+ int mac_offset;
|
||||
+ u32 mac_inc = 0;
|
||||
+ int i;
|
||||
+ struct mtd_info *the_mtd;
|
||||
+ size_t flash_readlen;
|
||||
+ const __be32 *list;
|
||||
+ const char *part;
|
||||
+ phandle phandle;
|
||||
+
|
||||
+ list = of_get_property(np, "ath,eep-flash", &i);
|
||||
+ if (!list || (i != (2 * sizeof(*list))))
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ phandle = be32_to_cpup(list++);
|
||||
+ if (phandle)
|
||||
+ mtd_np = of_find_node_by_phandle(phandle);
|
||||
+
|
||||
+ if (!mtd_np)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ part = of_get_property(mtd_np, "label", NULL);
|
||||
+ if (!part)
|
||||
+ part = mtd_np->name;
|
||||
+
|
||||
+ the_mtd = get_mtd_device_nm(part);
|
||||
+ if (IS_ERR(the_mtd))
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL);
|
||||
+
|
||||
+ i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1,
|
||||
+ &flash_readlen, (void *) ath5k_pdata.eeprom_data);
|
||||
+
|
||||
+ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
|
||||
+ size_t mac_readlen;
|
||||
+ mtd_read(the_mtd, mac_offset, 6, &mac_readlen,
|
||||
+ (void *) athxk_eeprom_mac);
|
||||
+ }
|
||||
+ put_mtd_device(the_mtd);
|
||||
+
|
||||
+ if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) {
|
||||
+ dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ if (of_find_property(np, "ath,eep-swap", NULL))
|
||||
+ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)
|
||||
+ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]);
|
||||
+
|
||||
+ if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac())
|
||||
+ ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac());
|
||||
+
|
||||
+ if (!is_valid_ether_addr(athxk_eeprom_mac)) {
|
||||
+ dev_warn(&pdev->dev, "using random mac\n");
|
||||
+ random_ether_addr(athxk_eeprom_mac);
|
||||
+ }
|
||||
+
|
||||
+ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
|
||||
+ athxk_eeprom_mac[5] += mac_inc;
|
||||
+
|
||||
+ ath5k_pdata.macaddr = athxk_eeprom_mac;
|
||||
+ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
|
||||
+
|
||||
+ dev_info(&pdev->dev, "loaded ath5k eeprom\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct of_device_id ath5k_eeprom_ids[] = {
|
||||
+ { .compatible = "ath5k,eeprom" },
|
||||
+ { }
|
||||
+};
|
||||
+
|
||||
+static struct platform_driver ath5k_eeprom_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "ath5k,eeprom",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = of_match_ptr(ath5k_eeprom_ids),
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init of_ath5k_eeprom_init(void)
|
||||
+{
|
||||
+ int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
|
||||
+
|
||||
+ if (ret)
|
||||
+ ath5k_eep_load = 1;
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int __init of_ath5k_eeprom_init_late(void)
|
||||
+{
|
||||
+ if (!ath5k_eep_load)
|
||||
+ return 0;
|
||||
+
|
||||
+ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
|
||||
+}
|
||||
+late_initcall(of_ath5k_eeprom_init_late);
|
||||
+subsys_initcall(of_ath5k_eeprom_init);
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/lantiq/xway/eth_mac.c
|
||||
@@ -0,0 +1,25 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/if_ether.h>
|
||||
+
|
||||
+static u8 eth_mac[6];
|
||||
+static int eth_mac_set;
|
||||
+
|
||||
+const u8* ltq_get_eth_mac(void)
|
||||
+{
|
||||
+ return eth_mac;
|
||||
+}
|
||||
+
|
||||
+static int __init setup_ethaddr(char *str)
|
||||
+{
|
||||
+ eth_mac_set = mac_pton(str, eth_mac);
|
||||
+ return !eth_mac_set;
|
||||
+}
|
||||
+early_param("ethaddr", setup_ethaddr);
|
||||
--- a/drivers/net/ethernet/lantiq_etop.c
|
||||
+++ b/drivers/net/ethernet/lantiq_etop.c
|
||||
@@ -840,7 +840,11 @@ ltq_etop_init(struct net_device *dev)
|
||||
if (err)
|
||||
goto err_hw;
|
||||
|
||||
- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
|
||||
+ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN);
|
||||
+
|
||||
+ if (priv->mac && !is_valid_ether_addr(mac.sa_data))
|
||||
+ memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
|
||||
+
|
||||
if (!is_valid_ether_addr(mac.sa_data)) {
|
||||
pr_warn("etop: invalid MAC, using random\n");
|
||||
eth_random_addr(mac.sa_data);
|
||||
@ -1,35 +0,0 @@ |
||||
--- a/drivers/usb/dwc2/platform.c
|
||||
+++ b/drivers/usb/dwc2/platform.c
|
||||
@@ -42,6 +42,7 @@
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/mutex.h>
|
||||
+#include <linux/of_gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_data/s3c-hsotg.h>
|
||||
@@ -336,6 +337,7 @@ static int dwc2_driver_probe(struct plat
|
||||
struct resource *res;
|
||||
int retval;
|
||||
int irq;
|
||||
+ int gpio_count;
|
||||
|
||||
match = of_match_device(dwc2_of_match_table, &dev->dev);
|
||||
if (match && match->data) {
|
||||
@@ -352,6 +354,16 @@ static int dwc2_driver_probe(struct plat
|
||||
defparams.dma_desc_enable = 0;
|
||||
}
|
||||
|
||||
+ gpio_count = of_gpio_count(dev->dev.of_node);
|
||||
+ while (gpio_count > 0) {
|
||||
+ enum of_gpio_flags flags;
|
||||
+ int gpio = of_get_gpio_flags(dev->dev.of_node, --gpio_count, &flags);
|
||||
+ if (gpio_request(gpio, "usb"))
|
||||
+ continue;
|
||||
+ dev_info(&dev->dev, "requested GPIO %d\n", gpio);
|
||||
+ gpio_direction_output(gpio, (flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
|
||||
+ }
|
||||
+
|
||||
hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
|
||||
if (!hsotg)
|
||||
return -ENOMEM;
|
||||
@ -1,23 +0,0 @@ |
||||
From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Fri, 3 Jun 2016 13:12:20 +0200
|
||||
Subject: [PATCH] arch: mips: increase io_space_limit
|
||||
|
||||
this value comes from x86 and breaks some pci devices
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
arch/mips/include/asm/io.h | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/mips/include/asm/io.h
|
||||
+++ b/arch/mips/include/asm/io.h
|
||||
@@ -50,7 +50,7 @@
|
||||
|
||||
/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
|
||||
|
||||
-#define IO_SPACE_LIMIT 0xffff
|
||||
+#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
/*
|
||||
* On MIPS I/O ports are memory mapped, so we access them using normal
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,28 +0,0 @@ |
||||
From 57b588c950b7e04e0f22393ad439299ba4fda9c3 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 26 Nov 2015 11:00:09 +0100
|
||||
Subject: [PATCH] pinctrl/lantiq: Fix GPIO Setup of GPIO Port3
|
||||
|
||||
Some special handling of GPIO Port 3 is needed because of
|
||||
some hardware thingofabob.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Signed-off-by: Martin Schiller <mschiller@tdt.de>
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
drivers/pinctrl/pinctrl-xway.c | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
--- a/drivers/pinctrl/pinctrl-xway.c
|
||||
+++ b/drivers/pinctrl/pinctrl-xway.c
|
||||
@@ -1570,6 +1570,10 @@ static int xway_gpio_dir_out(struct gpio
|
||||
{
|
||||
struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
|
||||
|
||||
+ if (PORT(pin) == PORT3)
|
||||
+ gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin));
|
||||
+ else
|
||||
+ gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin));
|
||||
gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
|
||||
xway_gpio_set(chip, pin, val);
|
||||
|
||||
@ -1,28 +0,0 @@ |
||||
From c9f294ff6584782d20b4a766901a9cff7398bb20 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 4 Jan 2016 22:27:57 +0100
|
||||
Subject: [PATCH] pinctrl: lantiq: 2 pins have the wrong mux list
|
||||
|
||||
The latest vendor SDK contained this patch.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
drivers/pinctrl/pinctrl-xway.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/pinctrl/pinctrl-xway.c
|
||||
+++ b/drivers/pinctrl/pinctrl-xway.c
|
||||
@@ -160,10 +160,10 @@ static const struct ltq_mfp_pin xway_mfp
|
||||
MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE),
|
||||
MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
|
||||
MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
|
||||
- MFP_XWAY(GPIO44, GPIO, NONE, SIN, GPHY),
|
||||
+ MFP_XWAY(GPIO44, GPIO, MII, SIN, GPHY),
|
||||
MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN),
|
||||
MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN),
|
||||
- MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN),
|
||||
+ MFP_XWAY(GPIO47, GPIO, MII, GPHY, SIN),
|
||||
MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
|
||||
MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
|
||||
MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
|
||||
@ -1,78 +0,0 @@ |
||||
--- a/arch/mips/lantiq/irq.c
|
||||
+++ b/arch/mips/lantiq/irq.c
|
||||
@@ -67,7 +67,7 @@ int gic_present;
|
||||
#endif
|
||||
|
||||
static int exin_avail;
|
||||
-static struct resource ltq_eiu_irq[MAX_EIU];
|
||||
+static u32 ltq_eiu_irq[MAX_EIU];
|
||||
static void __iomem *ltq_icu_membase[MAX_IM];
|
||||
static void __iomem *ltq_eiu_membase;
|
||||
static struct irq_domain *ltq_domain;
|
||||
@@ -76,7 +76,7 @@ static int ltq_perfcount_irq;
|
||||
int ltq_eiu_get_irq(int exin)
|
||||
{
|
||||
if (exin < exin_avail)
|
||||
- return ltq_eiu_irq[exin].start;
|
||||
+ return ltq_eiu_irq[exin];
|
||||
return -1;
|
||||
}
|
||||
|
||||
@@ -128,7 +128,7 @@ static int ltq_eiu_settype(struct irq_da
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
- if (d->hwirq == ltq_eiu_irq[i].start) {
|
||||
+ if (d->hwirq == ltq_eiu_irq[i]) {
|
||||
int val = 0;
|
||||
int edge = 0;
|
||||
|
||||
@@ -176,7 +176,7 @@ static unsigned int ltq_startup_eiu_irq(
|
||||
|
||||
ltq_enable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
- if (d->hwirq == ltq_eiu_irq[i].start) {
|
||||
+ if (d->hwirq == ltq_eiu_irq[i]) {
|
||||
/* by default we are low level triggered */
|
||||
ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
|
||||
/* clear all pending */
|
||||
@@ -198,7 +198,7 @@ static void ltq_shutdown_eiu_irq(struct
|
||||
|
||||
ltq_disable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
- if (d->hwirq == ltq_eiu_irq[i].start) {
|
||||
+ if (d->hwirq == ltq_eiu_irq[i]) {
|
||||
/* disable */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
|
||||
LTQ_EIU_EXIN_INEN);
|
||||
@@ -343,10 +343,10 @@ static int icu_map(struct irq_domain *d,
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < exin_avail; i++)
|
||||
- if (hw == ltq_eiu_irq[i].start)
|
||||
+ if (hw == ltq_eiu_irq[i])
|
||||
chip = <q_eiu_type;
|
||||
|
||||
- irq_set_chip_and_handler(hw, chip, handle_level_irq);
|
||||
+ irq_set_chip_and_handler(irq, chip, handle_level_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -441,14 +441,14 @@ int __init icu_of_init(struct device_nod
|
||||
eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
|
||||
if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
|
||||
/* find out how many external irq sources we have */
|
||||
- exin_avail = of_irq_count(eiu_node);
|
||||
+ exin_avail = of_property_count_u32_elems(eiu_node, "lantiq,eiu-irqs");
|
||||
|
||||
if (exin_avail > MAX_EIU)
|
||||
exin_avail = MAX_EIU;
|
||||
|
||||
- ret = of_irq_to_resource_table(eiu_node,
|
||||
+ ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
|
||||
ltq_eiu_irq, exin_avail);
|
||||
- if (ret != exin_avail)
|
||||
+ if (ret)
|
||||
panic("failed to load external irq resources");
|
||||
|
||||
if (!request_mem_region(res.start, resource_size(&res),
|
||||
@ -1,27 +0,0 @@ |
||||
--- a/drivers/mtd/nand/plat_nand.c
|
||||
+++ b/drivers/mtd/nand/plat_nand.c
|
||||
@@ -31,6 +31,7 @@ static int plat_nand_probe(struct platfo
|
||||
{
|
||||
struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev);
|
||||
struct mtd_part_parser_data ppdata;
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
struct plat_nand_data *data;
|
||||
struct resource *res;
|
||||
const char **part_types;
|
||||
@@ -58,6 +59,7 @@ static int plat_nand_probe(struct platfo
|
||||
return PTR_ERR(data->io_base);
|
||||
|
||||
data->chip.priv = &data;
|
||||
+ data->chip.flash_node = np;
|
||||
data->mtd.priv = &data->chip;
|
||||
data->mtd.dev.parent = &pdev->dev;
|
||||
|
||||
@@ -105,7 +107,7 @@ static int plat_nand_probe(struct platfo
|
||||
|
||||
part_types = pdata->chip.part_probe_types;
|
||||
|
||||
- ppdata.of_node = pdev->dev.of_node;
|
||||
+ ppdata.of_node = np;
|
||||
err = mtd_device_parse_register(&data->mtd, part_types, &ppdata,
|
||||
pdata->chip.partitions,
|
||||
pdata->chip.nr_partitions);
|
||||
@ -1,23 +0,0 @@ |
||||
--- a/arch/mips/lantiq/xway/reset.c
|
||||
+++ b/arch/mips/lantiq/xway/reset.c
|
||||
@@ -301,12 +301,6 @@ static void ltq_machine_halt(void)
|
||||
unreachable();
|
||||
}
|
||||
|
||||
-static void ltq_machine_power_off(void)
|
||||
-{
|
||||
- local_irq_disable();
|
||||
- unreachable();
|
||||
-}
|
||||
-
|
||||
static void ltq_usb_init(void)
|
||||
{
|
||||
/* Power for USB cores 1 & 2 */
|
||||
@@ -379,7 +373,6 @@ static int __init mips_reboot_setup(void
|
||||
|
||||
_machine_restart = ltq_machine_restart;
|
||||
_machine_halt = ltq_machine_halt;
|
||||
- pm_power_off = ltq_machine_power_off;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,87 +0,0 @@ |
||||
From: Felix Fietkau <nbd@nbd.name>
|
||||
Date: Thu, 19 Jan 2017 12:14:44 +0100
|
||||
Subject: [PATCH] MIPS: Lantiq: Fix cascaded IRQ setup
|
||||
|
||||
With the IRQ stack changes integrated, the XRX200 devices started
|
||||
emitting a constant stream of kernel messages like this:
|
||||
|
||||
[ 565.415310] Spurious IRQ: CAUSE=0x1100c300
|
||||
|
||||
This appears to be caused by IP0 firing for some reason without being
|
||||
handled. Fix this by setting up IP2-6 as a proper chained IRQ handler and
|
||||
calling do_IRQ for all MIPS CPU interrupts.
|
||||
|
||||
Cc: john@phrozen.org
|
||||
Cc: stable@vger.kernel.org
|
||||
Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
||||
---
|
||||
|
||||
--- a/arch/mips/lantiq/irq.c
|
||||
+++ b/arch/mips/lantiq/irq.c
|
||||
@@ -271,6 +271,11 @@ static void ltq_hw5_irqdispatch(void)
|
||||
DEFINE_HWx_IRQDISPATCH(5)
|
||||
#endif
|
||||
|
||||
+static void ltq_hw_irq_handler(struct irq_desc *desc)
|
||||
+{
|
||||
+ ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
|
||||
+}
|
||||
+
|
||||
#ifdef CONFIG_MIPS_MT_SMP
|
||||
void __init arch_init_ipiirq(int irq, struct irqaction *action)
|
||||
{
|
||||
@@ -315,23 +320,19 @@ static struct irqaction irq_call = {
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
- unsigned int i;
|
||||
+ int irq;
|
||||
|
||||
- if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
|
||||
- do_IRQ(MIPS_CPU_TIMER_IRQ);
|
||||
- goto out;
|
||||
- } else {
|
||||
- for (i = 0; i < MAX_IM; i++) {
|
||||
- if (pending & (CAUSEF_IP2 << i)) {
|
||||
- ltq_hw_irqdispatch(i);
|
||||
- goto out;
|
||||
- }
|
||||
- }
|
||||
+ if (!pending) {
|
||||
+ spurious_interrupt();
|
||||
+ return;
|
||||
}
|
||||
- pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
|
||||
|
||||
-out:
|
||||
- return;
|
||||
+ pending >>= CAUSEB_IP;
|
||||
+ while (pending) {
|
||||
+ irq = fls(pending) - 1;
|
||||
+ do_IRQ(MIPS_CPU_IRQ_BASE + irq);
|
||||
+ pending &= ~BIT(irq);
|
||||
+ }
|
||||
}
|
||||
|
||||
static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
||||
@@ -356,11 +357,6 @@ static const struct irq_domain_ops irq_d
|
||||
.map = icu_map,
|
||||
};
|
||||
|
||||
-static struct irqaction cascade = {
|
||||
- .handler = no_action,
|
||||
- .name = "cascade",
|
||||
-};
|
||||
-
|
||||
int __init icu_of_init(struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
struct device_node *eiu_node;
|
||||
@@ -392,7 +388,7 @@ int __init icu_of_init(struct device_nod
|
||||
mips_cpu_irq_init();
|
||||
|
||||
for (i = 0; i < MAX_IM; i++)
|
||||
- setup_irq(i + 2, &cascade);
|
||||
+ irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
|
||||
|
||||
if (cpu_has_vint) {
|
||||
pr_info("Setting up vectored interrupts\n");
|
||||
@ -1,78 +0,0 @@ |
||||
From 6c0c0951bbf8c2c216675fe277fba4c42aa0a2bf Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Antti=20Sepp=C3=A4l=C3=A4?= <a.seppala@gmail.com>
|
||||
Date: Sat, 27 Feb 2016 12:31:24 +0200
|
||||
Subject: [PATCH] usb: dwc2: Add support for Lantiq ARX and XRX SoCs
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Add support for Lantiq ARX and XRX SoC families to the dwc2 driver.
|
||||
|
||||
Acked-by: John Youn <johnyoun@synopsys.com>
|
||||
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
|
||||
Signed-off-by: Felipe Balbi <balbi@kernel.org>
|
||||
---
|
||||
Documentation/devicetree/bindings/usb/dwc2.txt | 2 ++
|
||||
drivers/usb/dwc2/platform.c | 34 ++++++++++++++++++++++++++
|
||||
2 files changed, 36 insertions(+)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
|
||||
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
|
||||
@@ -7,6 +7,8 @@ Required properties:
|
||||
- rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
|
||||
- "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
|
||||
- "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
|
||||
+ - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
|
||||
+ - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
|
||||
- snps,dwc2: A generic DWC2 USB controller with default parameters.
|
||||
- reg : Should contain 1 register range (address and length)
|
||||
- interrupts : Should contain 1 interrupt
|
||||
--- a/drivers/usb/dwc2/platform.c
|
||||
+++ b/drivers/usb/dwc2/platform.c
|
||||
@@ -116,6 +116,37 @@ static const struct dwc2_core_params par
|
||||
.hibernation = -1,
|
||||
};
|
||||
|
||||
+static const struct dwc2_core_params params_ltq = {
|
||||
+ .otg_cap = 2, /* non-HNP/non-SRP */
|
||||
+ .otg_ver = -1,
|
||||
+ .dma_enable = -1,
|
||||
+ .dma_desc_enable = -1,
|
||||
+ .speed = -1,
|
||||
+ .enable_dynamic_fifo = -1,
|
||||
+ .en_multiple_tx_fifo = -1,
|
||||
+ .host_rx_fifo_size = 288, /* 288 DWORDs */
|
||||
+ .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
|
||||
+ .host_perio_tx_fifo_size = 96, /* 96 DWORDs */
|
||||
+ .max_transfer_size = 65535,
|
||||
+ .max_packet_count = 511,
|
||||
+ .host_channels = -1,
|
||||
+ .phy_type = -1,
|
||||
+ .phy_utmi_width = -1,
|
||||
+ .phy_ulpi_ddr = -1,
|
||||
+ .phy_ulpi_ext_vbus = -1,
|
||||
+ .i2c_enable = -1,
|
||||
+ .ulpi_fs_ls = -1,
|
||||
+ .host_support_fs_ls_low_power = -1,
|
||||
+ .host_ls_low_power_phy_clk = -1,
|
||||
+ .ts_dline = -1,
|
||||
+ .reload_ctl = -1,
|
||||
+ .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
|
||||
+ GAHBCFG_HBSTLEN_SHIFT,
|
||||
+ .uframe_sched = -1,
|
||||
+ .external_id_pin_ctl = -1,
|
||||
+ .hibernation = -1,
|
||||
+};
|
||||
+
|
||||
static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(hsotg->dev);
|
||||
@@ -310,6 +341,8 @@ static int dwc2_driver_remove(struct pla
|
||||
static const struct of_device_id dwc2_of_match_table[] = {
|
||||
{ .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 },
|
||||
{ .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 },
|
||||
+ { .compatible = "lantiq,arx100-usb", .data = ¶ms_ltq },
|
||||
+ { .compatible = "lantiq,xrx200-usb", .data = ¶ms_ltq },
|
||||
{ .compatible = "snps,dwc2", .data = NULL },
|
||||
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
|
||||
{},
|
||||
@ -1,129 +0,0 @@ |
||||
From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Fri, 6 Jan 2017 17:55:24 +0100
|
||||
Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs
|
||||
|
||||
The size of the internal RAM of the DesignWare USB controller changed
|
||||
between the different Lantiq SoCs. We have the following sizes:
|
||||
|
||||
Amazon + Danube: 8 KByte
|
||||
Amazon SE + arx100: 2 KByte
|
||||
xrx200 + xrx300: 2.5 KByte
|
||||
|
||||
For Danube SoC we do not provide the params and let the driver decide
|
||||
to use sane defaults, for the Amazon SE and arx100 we use small fifos
|
||||
and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo.
|
||||
The auto detection of max_transfer_size and max_packet_count should
|
||||
work, so remove it.
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++-------
|
||||
1 file changed, 39 insertions(+), 7 deletions(-)
|
||||
|
||||
--- a/drivers/usb/dwc2/platform.c
|
||||
+++ b/drivers/usb/dwc2/platform.c
|
||||
@@ -116,7 +116,37 @@ static const struct dwc2_core_params par
|
||||
.hibernation = -1,
|
||||
};
|
||||
|
||||
-static const struct dwc2_core_params params_ltq = {
|
||||
+static const struct dwc2_core_params params_danube = {
|
||||
+ .otg_cap = 2, /* non-HNP/non-SRP */
|
||||
+ .otg_ver = -1,
|
||||
+ .dma_enable = -1,
|
||||
+ .dma_desc_enable = -1,
|
||||
+ .speed = -1,
|
||||
+ .enable_dynamic_fifo = -1,
|
||||
+ .en_multiple_tx_fifo = -1,
|
||||
+ .host_rx_fifo_size = -1,
|
||||
+ .host_nperio_tx_fifo_size = -1,
|
||||
+ .host_perio_tx_fifo_size = -1,
|
||||
+ .max_transfer_size = -1,
|
||||
+ .max_packet_count = -1,
|
||||
+ .host_channels = -1,
|
||||
+ .phy_type = -1,
|
||||
+ .phy_utmi_width = -1,
|
||||
+ .phy_ulpi_ddr = -1,
|
||||
+ .phy_ulpi_ext_vbus = -1,
|
||||
+ .i2c_enable = -1,
|
||||
+ .ulpi_fs_ls = -1,
|
||||
+ .host_support_fs_ls_low_power = -1,
|
||||
+ .host_ls_low_power_phy_clk = -1,
|
||||
+ .ts_dline = -1,
|
||||
+ .reload_ctl = -1,
|
||||
+ .ahbcfg = -1,
|
||||
+ .uframe_sched = -1,
|
||||
+ .external_id_pin_ctl = -1,
|
||||
+ .hibernation = -1,
|
||||
+};
|
||||
+
|
||||
+static const struct dwc2_core_params params_ase = {
|
||||
.otg_cap = 2, /* non-HNP/non-SRP */
|
||||
.otg_ver = -1,
|
||||
.dma_enable = -1,
|
||||
@@ -127,8 +157,38 @@ static const struct dwc2_core_params par
|
||||
.host_rx_fifo_size = 288, /* 288 DWORDs */
|
||||
.host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
|
||||
.host_perio_tx_fifo_size = 96, /* 96 DWORDs */
|
||||
- .max_transfer_size = 65535,
|
||||
- .max_packet_count = 511,
|
||||
+ .max_transfer_size = -1,
|
||||
+ .max_packet_count = -1,
|
||||
+ .host_channels = -1,
|
||||
+ .phy_type = -1,
|
||||
+ .phy_utmi_width = -1,
|
||||
+ .phy_ulpi_ddr = -1,
|
||||
+ .phy_ulpi_ext_vbus = -1,
|
||||
+ .i2c_enable = -1,
|
||||
+ .ulpi_fs_ls = -1,
|
||||
+ .host_support_fs_ls_low_power = -1,
|
||||
+ .host_ls_low_power_phy_clk = -1,
|
||||
+ .ts_dline = -1,
|
||||
+ .reload_ctl = -1,
|
||||
+ .ahbcfg = -1,
|
||||
+ .uframe_sched = -1,
|
||||
+ .external_id_pin_ctl = -1,
|
||||
+ .hibernation = -1,
|
||||
+};
|
||||
+
|
||||
+static const struct dwc2_core_params params_xrx200 = {
|
||||
+ .otg_cap = 2, /* non-HNP/non-SRP */
|
||||
+ .otg_ver = -1,
|
||||
+ .dma_enable = -1,
|
||||
+ .dma_desc_enable = -1,
|
||||
+ .speed = -1,
|
||||
+ .enable_dynamic_fifo = -1,
|
||||
+ .en_multiple_tx_fifo = -1,
|
||||
+ .host_rx_fifo_size = 288, /* 288 DWORDs */
|
||||
+ .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
|
||||
+ .host_perio_tx_fifo_size = 136, /* 136 DWORDs */
|
||||
+ .max_transfer_size = -1,
|
||||
+ .max_packet_count = -1,
|
||||
.host_channels = -1,
|
||||
.phy_type = -1,
|
||||
.phy_utmi_width = -1,
|
||||
@@ -140,8 +200,7 @@ static const struct dwc2_core_params par
|
||||
.host_ls_low_power_phy_clk = -1,
|
||||
.ts_dline = -1,
|
||||
.reload_ctl = -1,
|
||||
- .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
|
||||
- GAHBCFG_HBSTLEN_SHIFT,
|
||||
+ .ahbcfg = -1,
|
||||
.uframe_sched = -1,
|
||||
.external_id_pin_ctl = -1,
|
||||
.hibernation = -1,
|
||||
@@ -341,8 +400,11 @@ static int dwc2_driver_remove(struct pla
|
||||
static const struct of_device_id dwc2_of_match_table[] = {
|
||||
{ .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 },
|
||||
{ .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 },
|
||||
- { .compatible = "lantiq,arx100-usb", .data = ¶ms_ltq },
|
||||
- { .compatible = "lantiq,xrx200-usb", .data = ¶ms_ltq },
|
||||
+ { .compatible = "lantiq,danube-usb", .data = ¶ms_danube },
|
||||
+ { .compatible = "lantiq,ase-usb", .data = ¶ms_ase },
|
||||
+ { .compatible = "lantiq,arx100-usb", .data = ¶ms_ase },
|
||||
+ { .compatible = "lantiq,xrx200-usb", .data = ¶ms_xrx200 },
|
||||
+ { .compatible = "lantiq,xrx300-usb", .data = ¶ms_xrx200 },
|
||||
{ .compatible = "snps,dwc2", .data = NULL },
|
||||
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
|
||||
{},
|
||||
@ -1,202 +0,0 @@ |
||||
From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Fri, 6 Jan 2017 17:40:12 +0100
|
||||
Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
|
||||
|
||||
This adds code to initialize the USB controller and PHY also on Danube,
|
||||
Amazon SE and AR10. This code is based on the Vendor driver from
|
||||
different UGW versions and compared to the hardware documentation.
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
arch/mips/lantiq/xway/reset.c | 120 ++++++++++++++++++++++++++++++----------
|
||||
arch/mips/lantiq/xway/sysctrl.c | 20 +++++++
|
||||
2 files changed, 110 insertions(+), 30 deletions(-)
|
||||
|
||||
--- a/arch/mips/lantiq/xway/reset.c
|
||||
+++ b/arch/mips/lantiq/xway/reset.c
|
||||
@@ -72,6 +72,8 @@
|
||||
#define RCU_USBCFG_HDSEL_BIT BIT(11)
|
||||
#define RCU_USBCFG_HOST_END_BIT BIT(10)
|
||||
#define RCU_USBCFG_SLV_END_BIT BIT(9)
|
||||
+#define RCU_USBCFG_SLV_END_BIT_AR9 BIT(17)
|
||||
+
|
||||
|
||||
/* USB reset bits */
|
||||
#define RCU_USBRESET 0x0010
|
||||
@@ -85,6 +87,8 @@
|
||||
|
||||
#define RCU_CFG1A 0x0038
|
||||
#define RCU_CFG1B 0x003C
|
||||
+#define RCU_CFG1_TX_PEE BIT(0)
|
||||
+#define RCU_CFG1_DIS_THR_SHIFT 15 /* Disconnect Threshold */
|
||||
|
||||
/* USB PMU devices */
|
||||
#define PMU_AHBM BIT(15)
|
||||
@@ -306,38 +310,91 @@ static void ltq_usb_init(void)
|
||||
/* Power for USB cores 1 & 2 */
|
||||
ltq_pmu_enable(PMU_AHBM);
|
||||
ltq_pmu_enable(PMU_USB0);
|
||||
- ltq_pmu_enable(PMU_USB1);
|
||||
|
||||
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
|
||||
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
|
||||
+ if (of_machine_is_compatible("lantiq,ar10") ||
|
||||
+ of_machine_is_compatible("lantiq,grx390") ||
|
||||
+ of_machine_is_compatible("lantiq,ar9") ||
|
||||
+ of_machine_is_compatible("lantiq,vr9"))
|
||||
+ ltq_pmu_enable(PMU_USB1);
|
||||
+
|
||||
+ if (of_machine_is_compatible("lantiq,vr9") ||
|
||||
+ of_machine_is_compatible("lantiq,ar10")) {
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | RCU_CFG1_TX_PEE |
|
||||
+ 7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1A);
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | RCU_CFG1_TX_PEE |
|
||||
+ 7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1B);
|
||||
+ }
|
||||
|
||||
/* Enable USB PHY power for cores 1 & 2 */
|
||||
ltq_pmu_enable(PMU_USB0_P);
|
||||
- ltq_pmu_enable(PMU_USB1_P);
|
||||
+ if (of_machine_is_compatible("lantiq,ar10") ||
|
||||
+ of_machine_is_compatible("lantiq,grx390") ||
|
||||
+ of_machine_is_compatible("lantiq,ar9") ||
|
||||
+ of_machine_is_compatible("lantiq,vr9"))
|
||||
+ ltq_pmu_enable(PMU_USB1_P);
|
||||
+
|
||||
+ if (of_machine_is_compatible("lantiq,ase") ||
|
||||
+ of_machine_is_compatible("lantiq,danube")) {
|
||||
+ /* Configure cores to host mode */
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
|
||||
+ RCU_USB1CFG);
|
||||
+
|
||||
+ /* Select DMA endianness (Host-endian: big-endian) */
|
||||
+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
|
||||
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
|
||||
+ }
|
||||
+
|
||||
+ if (of_machine_is_compatible("lantiq,ar9")) {
|
||||
+ /* Configure cores to host mode */
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
|
||||
+ RCU_USB1CFG);
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
|
||||
+ RCU_USB2CFG);
|
||||
+
|
||||
+ /* Select DMA endianness (Host-endian: big-endian) */
|
||||
+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9)
|
||||
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
|
||||
+ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9)
|
||||
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
|
||||
+ }
|
||||
+
|
||||
+ if (of_machine_is_compatible("lantiq,vr9") ||
|
||||
+ of_machine_is_compatible("lantiq,ar10")) {
|
||||
+ /* Configure cores to host mode */
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
|
||||
+ RCU_USB1CFG);
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
|
||||
+ RCU_USB2CFG);
|
||||
+
|
||||
+ /* Select DMA endianness (Host-endian: big-endian) */
|
||||
+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
|
||||
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
|
||||
+ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
|
||||
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
|
||||
+ }
|
||||
+
|
||||
+ if (of_machine_is_compatible("lantiq,ar9")) {
|
||||
+ /* Hard reset USB state machines */
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET)
|
||||
+ | USBRESET_BIT | BIT(28), RCU_USBRESET);
|
||||
+ udelay(50 * 1000);
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET)
|
||||
+ & ~(USBRESET_BIT | BIT(28)), RCU_USBRESET);
|
||||
+ } else {
|
||||
+ /* Hard reset USB state machines */
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
|
||||
+ udelay(50 * 1000);
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
|
||||
+ }
|
||||
|
||||
- /* Configure cores to host mode */
|
||||
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
|
||||
- RCU_USB1CFG);
|
||||
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
|
||||
- RCU_USB2CFG);
|
||||
-
|
||||
- /* Select DMA endianness (Host-endian: big-endian) */
|
||||
- ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
|
||||
- | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
|
||||
- ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
|
||||
- | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
|
||||
-
|
||||
- /* Hard reset USB state machines */
|
||||
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
|
||||
- udelay(50 * 1000);
|
||||
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
|
||||
-
|
||||
- /* Soft reset USB state machines */
|
||||
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
|
||||
- | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
|
||||
- udelay(50 * 1000);
|
||||
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
|
||||
- & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
|
||||
+ if (of_machine_is_compatible("lantiq,vr9")) {
|
||||
+ /* Soft reset USB state machines */
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
|
||||
+ | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
|
||||
+ udelay(50 * 1000);
|
||||
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
|
||||
+ & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
|
||||
+ }
|
||||
}
|
||||
|
||||
static int __init mips_reboot_setup(void)
|
||||
@@ -363,8 +420,11 @@ static int __init mips_reboot_setup(void
|
||||
if (!ltq_rcu_membase)
|
||||
panic("Failed to remap core memory");
|
||||
|
||||
- if (of_machine_is_compatible("lantiq,ar9") ||
|
||||
- of_machine_is_compatible("lantiq,vr9"))
|
||||
+ if (of_machine_is_compatible("lantiq,danube") ||
|
||||
+ of_machine_is_compatible("lantiq,ase") ||
|
||||
+ of_machine_is_compatible("lantiq,ar9") ||
|
||||
+ of_machine_is_compatible("lantiq,vr9") ||
|
||||
+ of_machine_is_compatible("lantiq,ar10"))
|
||||
ltq_usb_init();
|
||||
|
||||
if (of_machine_is_compatible("lantiq,vr9"))
|
||||
--- a/arch/mips/lantiq/xway/sysctrl.c
|
||||
+++ b/arch/mips/lantiq/xway/sysctrl.c
|
||||
@@ -254,6 +254,25 @@ static void pmu_disable(struct clk *clk)
|
||||
pr_warn("deactivating PMU module failed!");
|
||||
}
|
||||
|
||||
+static void usb_set_clock(void)
|
||||
+{
|
||||
+ unsigned int val = ltq_cgu_r32(ifccr);
|
||||
+
|
||||
+ if (of_machine_is_compatible("lantiq,ar10") ||
|
||||
+ of_machine_is_compatible("lantiq,grx390")) {
|
||||
+ val &= ~0x03; /* XTAL divided by 3 */
|
||||
+ } else if (of_machine_is_compatible("lantiq,ar9") ||
|
||||
+ of_machine_is_compatible("lantiq,vr9")) {
|
||||
+ /* TODO: this depends on the XTAL frequency */
|
||||
+ val |= 0x03; /* XTAL divided by 3 */
|
||||
+ } else if (of_machine_is_compatible("lantiq,ase")) {
|
||||
+ val |= 0x20; /* from XTAL */
|
||||
+ } else if (of_machine_is_compatible("lantiq,danube")) {
|
||||
+ val |= 0x30; /* 12 MHz, generated from 36 MHz */
|
||||
+ }
|
||||
+ ltq_cgu_w32(val, ifccr);
|
||||
+}
|
||||
+
|
||||
/* the pci enable helper */
|
||||
static int pci_enable(struct clk *clk)
|
||||
{
|
||||
@@ -608,4 +627,5 @@ void __init ltq_soc_init(void)
|
||||
|
||||
if (of_machine_is_compatible("lantiq,vr9"))
|
||||
xbar_fpi_burst_disable();
|
||||
+ usb_set_clock();
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,93 +0,0 @@ |
||||
--- a/drivers/mtd/ofpart.c
|
||||
+++ b/drivers/mtd/ofpart.c
|
||||
@@ -25,6 +25,38 @@ static bool node_has_compatible(struct d
|
||||
return of_get_property(pp, "compatible", NULL);
|
||||
}
|
||||
|
||||
+static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master,
|
||||
+ loff_t offset)
|
||||
+{
|
||||
+ static uint8_t root_id;
|
||||
+ int err, len;
|
||||
+
|
||||
+ err = mtd_read(master, offset, 0x01, &len, &root_id);
|
||||
+
|
||||
+ if (mtd_is_bitflip(err) || !err)
|
||||
+ return &root_id;
|
||||
+
|
||||
+ return NULL;
|
||||
+}
|
||||
+
|
||||
+static void brnboot_set_active_root_part(struct mtd_partition *pparts,
|
||||
+ struct device_node **part_nodes,
|
||||
+ int nr_parts,
|
||||
+ uint8_t *root_id)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < nr_parts; i++) {
|
||||
+ int part_root_id;
|
||||
+
|
||||
+ if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id)
|
||||
+ && part_root_id == *root_id) {
|
||||
+ pparts[i].name = "firmware";
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static int parse_ofpart_partitions(struct mtd_info *master,
|
||||
struct mtd_partition **pparts,
|
||||
struct mtd_part_parser_data *data)
|
||||
@@ -35,7 +67,8 @@ static int parse_ofpart_partitions(struc
|
||||
struct device_node *pp;
|
||||
int nr_parts, i, ret = 0;
|
||||
bool dedicated = true;
|
||||
-
|
||||
+ uint8_t *proot_id = NULL;
|
||||
+ struct device_node **part_nodes;
|
||||
|
||||
if (!data)
|
||||
return 0;
|
||||
@@ -73,7 +106,9 @@ static int parse_ofpart_partitions(struc
|
||||
return 0;
|
||||
|
||||
*pparts = kzalloc(nr_parts * sizeof(**pparts), GFP_KERNEL);
|
||||
- if (!*pparts)
|
||||
+ part_nodes = kzalloc(nr_parts * sizeof(*part_nodes), GFP_KERNEL);
|
||||
+
|
||||
+ if (!*pparts || !part_nodes)
|
||||
return -ENOMEM;
|
||||
|
||||
i = 0;
|
||||
@@ -121,12 +156,22 @@ static int parse_ofpart_partitions(struc
|
||||
if (of_get_property(pp, "lock", &len))
|
||||
(*pparts)[i].mask_flags |= MTD_POWERUP_LOCK;
|
||||
|
||||
+ if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector"))
|
||||
+ proot_id = brnboot_get_selected_root_part(master, (*pparts)[i].offset);
|
||||
+
|
||||
+ part_nodes[i] = pp;
|
||||
+
|
||||
i++;
|
||||
}
|
||||
|
||||
if (!nr_parts)
|
||||
goto ofpart_none;
|
||||
|
||||
+ if (proot_id)
|
||||
+ brnboot_set_active_root_part(*pparts, part_nodes, nr_parts, proot_id);
|
||||
+
|
||||
+ kfree(part_nodes);
|
||||
+
|
||||
return nr_parts;
|
||||
|
||||
ofpart_fail:
|
||||
@@ -136,6 +181,7 @@ ofpart_fail:
|
||||
ofpart_none:
|
||||
of_node_put(pp);
|
||||
kfree(*pparts);
|
||||
+ kfree(part_nodes);
|
||||
*pparts = NULL;
|
||||
return ret;
|
||||
}
|
||||
@ -1,48 +0,0 @@ |
||||
From a32285ed4ba970b868b7fb49b716d776f4410ef6 Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Sat, 19 Mar 2016 16:52:46 +0100
|
||||
Subject: [PATCH] MIPS: lantiq: add support for device tree file from boot
|
||||
loader
|
||||
|
||||
This fetches the device tree file like it is specified in the MIPS UHI
|
||||
interface if one was found. This is also used when the device tree file
|
||||
was appended to the kernel image with cat.
|
||||
This code is copied from arch/mips/bmips/setup.c.
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
arch/mips/lantiq/prom.c | 13 +++++++++++--
|
||||
1 file changed, 11 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/mips/lantiq/prom.c
|
||||
+++ b/arch/mips/lantiq/prom.c
|
||||
@@ -65,6 +65,8 @@ static void __init prom_init_cmdline(voi
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
+ void *dtb;
|
||||
+
|
||||
ioport_resource.start = IOPORT_RESOURCE_START;
|
||||
ioport_resource.end = IOPORT_RESOURCE_END;
|
||||
iomem_resource.start = IOMEM_RESOURCE_START;
|
||||
@@ -72,11 +74,18 @@ void __init plat_mem_setup(void)
|
||||
|
||||
set_io_port_base((unsigned long) KSEG1);
|
||||
|
||||
+ if (fw_arg0 == -2) /* UHI interface */
|
||||
+ dtb = (void *)fw_arg1;
|
||||
+ else if (__dtb_start != __dtb_end)
|
||||
+ dtb = (void *)__dtb_start;
|
||||
+ else
|
||||
+ panic("no dtb found");
|
||||
+
|
||||
/*
|
||||
- * Load the builtin devicetree. This causes the chosen node to be
|
||||
+ * Load the devicetree. This causes the chosen node to be
|
||||
* parsed resulting in our memory appearing
|
||||
*/
|
||||
- __dt_setup_arch(__dtb_start);
|
||||
+ __dt_setup_arch(dtb);
|
||||
}
|
||||
|
||||
void __init device_tree_init(void)
|
||||
@ -1,37 +0,0 @@ |
||||
From 8cfe01de7d5c974165c1383fcc9e1dad6953341d Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Sat, 19 Mar 2016 17:06:00 +0100
|
||||
Subject: [PATCH 2/2] MIPS: lantiq: make it possible to build in no device tree
|
||||
|
||||
Now it is possible to build in no device tree at all and depend on the
|
||||
boot loader providing one or someone concatenating a device tree to the
|
||||
end of the image.
|
||||
|
||||
This was copied from arch/mips/bmips/Kconfig
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
arch/mips/lantiq/Kconfig | 12 +++++++++++-
|
||||
1 file changed, 11 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/mips/lantiq/Kconfig
|
||||
+++ b/arch/mips/lantiq/Kconfig
|
||||
@@ -26,7 +26,17 @@ config SOC_FALCON
|
||||
endchoice
|
||||
|
||||
choice
|
||||
- prompt "Devicetree"
|
||||
+ prompt "Built-in device tree"
|
||||
+ help
|
||||
+ Legacy bootloaders do not pass a DTB pointer to the kernel, so
|
||||
+ if a "wrapper" is not being used, the kernel will need to include
|
||||
+ a device tree that matches the target board.
|
||||
+
|
||||
+ The builtin DTB will only be used if the firmware does not supply
|
||||
+ a valid DTB.
|
||||
+
|
||||
+config LANTIQ_DT_NONE
|
||||
+ bool "None"
|
||||
|
||||
config DT_EASY50712
|
||||
bool "Easy50712"
|
||||
@ -1,166 +0,0 @@ |
||||
--- a/arch/mips/pci/ifxmips_pcie.c
|
||||
+++ b/arch/mips/pci/ifxmips_pcie.c
|
||||
@@ -18,6 +18,9 @@
|
||||
#include <linux/pci_regs.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
+#include <linux/of_gpio.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+
|
||||
#include "ifxmips_pcie.h"
|
||||
#include "ifxmips_pcie_reg.h"
|
||||
|
||||
@@ -40,6 +43,7 @@
|
||||
static DEFINE_SPINLOCK(ifx_pcie_lock);
|
||||
|
||||
u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
|
||||
+static int pcie_reset_gpio;
|
||||
|
||||
static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
|
||||
{
|
||||
@@ -82,6 +86,22 @@ void ifx_pcie_debug(const char *fmt, ...
|
||||
printk("%s", buf);
|
||||
}
|
||||
|
||||
+static inline void pcie_ep_gpio_rst_init(int pcie_port)
|
||||
+{
|
||||
+ gpio_direction_output(pcie_reset_gpio, 1);
|
||||
+ gpio_set_value(pcie_reset_gpio, 1);
|
||||
+}
|
||||
+
|
||||
+static inline void pcie_device_rst_assert(int pcie_port)
|
||||
+{
|
||||
+ gpio_set_value(pcie_reset_gpio, 0);
|
||||
+}
|
||||
+
|
||||
+static inline void pcie_device_rst_deassert(int pcie_port)
|
||||
+{
|
||||
+ mdelay(100);
|
||||
+ gpio_direction_output(pcie_reset_gpio, 1);
|
||||
+}
|
||||
|
||||
static inline int pcie_ltssm_enable(int pcie_port)
|
||||
{
|
||||
@@ -1045,8 +1065,9 @@ pcie_rc_initialize(int pcie_port)
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int __init ifx_pcie_bios_init(void)
|
||||
+static int ifx_pcie_bios_probe(struct platform_device *pdev)
|
||||
{
|
||||
+ struct device_node *node = pdev->dev.of_node;
|
||||
void __iomem *io_map_base;
|
||||
int pcie_port;
|
||||
int startup_port;
|
||||
@@ -1055,7 +1076,17 @@ static int __init ifx_pcie_bios_init(voi
|
||||
pcie_ahb_pmu_setup();
|
||||
|
||||
startup_port = IFX_PCIE_PORT0;
|
||||
-
|
||||
+
|
||||
+ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
|
||||
+ if (gpio_is_valid(pcie_reset_gpio)) {
|
||||
+ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset");
|
||||
+ if (ret) {
|
||||
+ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ gpio_direction_output(pcie_reset_gpio, 1);
|
||||
+ }
|
||||
+
|
||||
for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
|
||||
if (pcie_rc_initialize(pcie_port) == 0) {
|
||||
IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n",
|
||||
@@ -1067,6 +1098,7 @@ static int __init ifx_pcie_bios_init(voi
|
||||
return -ENOMEM;
|
||||
}
|
||||
ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
|
||||
+ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node);
|
||||
|
||||
register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
|
||||
/* XXX, clear error status */
|
||||
@@ -1083,6 +1115,30 @@ static int __init ifx_pcie_bios_init(voi
|
||||
|
||||
return 0;
|
||||
}
|
||||
+
|
||||
+static const struct of_device_id ifxmips_pcie_match[] = {
|
||||
+ { .compatible = "lantiq,pcie-xrx200" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, ifxmips_pcie_match);
|
||||
+
|
||||
+static struct platform_driver ltq_pci_driver = {
|
||||
+ .probe = ifx_pcie_bios_probe,
|
||||
+ .driver = {
|
||||
+ .name = "pcie-xrx200",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = ifxmips_pcie_match,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+int __init ifx_pcie_bios_init(void)
|
||||
+{
|
||||
+ int ret = platform_driver_register(<q_pci_driver);
|
||||
+ if (ret)
|
||||
+ pr_info("pcie-xrx200: Error registering platform driver!");
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
arch_initcall(ifx_pcie_bios_init);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
--- a/arch/mips/pci/ifxmips_pcie_vr9.h
|
||||
+++ b/arch/mips/pci/ifxmips_pcie_vr9.h
|
||||
@@ -22,8 +22,6 @@
|
||||
#include <linux/gpio.h>
|
||||
#include <lantiq_soc.h>
|
||||
|
||||
-#define IFX_PCIE_GPIO_RESET 494
|
||||
-
|
||||
#define IFX_REG_R32 ltq_r32
|
||||
#define IFX_REG_W32 ltq_w32
|
||||
#define CONFIG_IFX_PCIE_HW_SWAP
|
||||
@@ -53,21 +51,6 @@
|
||||
#define OUT ((volatile u32*)(IFX_GPIO + 0x0070))
|
||||
|
||||
|
||||
-static inline void pcie_ep_gpio_rst_init(int pcie_port)
|
||||
-{
|
||||
-
|
||||
- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset");
|
||||
- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
|
||||
- gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
|
||||
-
|
||||
-/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
||||
- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
||||
- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
||||
- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
||||
- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
||||
- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/
|
||||
-}
|
||||
-
|
||||
static inline void pcie_ahb_pmu_setup(void)
|
||||
{
|
||||
/* Enable AHB bus master/slave */
|
||||
@@ -180,20 +163,6 @@ static inline void pcie_phy_rst_deassert
|
||||
IFX_REG_W32(reg, IFX_RCU_RST_REQ);
|
||||
}
|
||||
|
||||
-static inline void pcie_device_rst_assert(int pcie_port)
|
||||
-{
|
||||
- gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
|
||||
-// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
||||
-}
|
||||
-
|
||||
-static inline void pcie_device_rst_deassert(int pcie_port)
|
||||
-{
|
||||
- mdelay(100);
|
||||
- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
|
||||
-// gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
|
||||
- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
||||
-}
|
||||
-
|
||||
static inline void pcie_core_pmu_setup(int pcie_port)
|
||||
{
|
||||
struct clk *clk;
|
||||
@ -1,180 +0,0 @@ |
||||
--- a/arch/mips/Kconfig
|
||||
+++ b/arch/mips/Kconfig
|
||||
@@ -2221,6 +2221,12 @@ config MIPS_VPE_LOADER
|
||||
Includes a loader for loading an elf relocatable object
|
||||
onto another VPE and running it.
|
||||
|
||||
+config IFX_VPE_EXT
|
||||
+ bool "IFX APRP Extensions"
|
||||
+ depends on MIPS_VPE_LOADER
|
||||
+ help
|
||||
+ IFX included extensions in APRP
|
||||
+
|
||||
config MIPS_VPE_LOADER_CMP
|
||||
bool
|
||||
default "y"
|
||||
--- a/arch/mips/include/asm/vpe.h
|
||||
+++ b/arch/mips/include/asm/vpe.h
|
||||
@@ -127,4 +127,13 @@ void cleanup_tc(struct tc *tc);
|
||||
|
||||
int __init vpe_module_init(void);
|
||||
void __exit vpe_module_exit(void);
|
||||
+
|
||||
+/* For the explanation of the APIs please refer the section "MT APRP Kernel
|
||||
+ * Programming" in AR9 SW Architecture Specification
|
||||
+ */
|
||||
+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags);
|
||||
+int32_t vpe1_sw_stop(uint32_t flags);
|
||||
+uint32_t vpe1_get_load_addr(uint32_t flags);
|
||||
+uint32_t vpe1_get_max_mem(uint32_t flags);
|
||||
+
|
||||
#endif /* _ASM_VPE_H */
|
||||
--- a/arch/mips/kernel/vpe-mt.c
|
||||
+++ b/arch/mips/kernel/vpe-mt.c
|
||||
@@ -29,6 +29,7 @@ int vpe_run(struct vpe *v)
|
||||
struct vpe_notifications *notifier;
|
||||
unsigned int vpeflags;
|
||||
struct tc *t;
|
||||
+ unsigned long physical_memsize = 0L;
|
||||
|
||||
/* check we are the Master VPE */
|
||||
local_irq_save(flags);
|
||||
@@ -417,6 +418,8 @@ int __init vpe_module_init(void)
|
||||
}
|
||||
|
||||
v->ntcs = hw_tcs - aprp_cpu_index();
|
||||
+ write_tc_c0_tcbind((read_tc_c0_tcbind() &
|
||||
+ ~TCBIND_CURVPE) | 1);
|
||||
|
||||
/* add the tc to the list of this vpe's tc's. */
|
||||
list_add(&t->tc, &v->tc);
|
||||
@@ -519,3 +522,47 @@ void __exit vpe_module_exit(void)
|
||||
release_vpe(v);
|
||||
}
|
||||
}
|
||||
+
|
||||
+#ifdef CONFIG_IFX_VPE_EXT
|
||||
+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags)
|
||||
+{
|
||||
+ enum vpe_state state;
|
||||
+ struct vpe *v = get_vpe(tclimit);
|
||||
+ struct vpe_notifications *not;
|
||||
+
|
||||
+ if (tcmask || flags) {
|
||||
+ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n");
|
||||
+ return -1;
|
||||
+ }
|
||||
+
|
||||
+ state = xchg(&v->state, VPE_STATE_INUSE);
|
||||
+ if (state != VPE_STATE_UNUSED) {
|
||||
+ vpe_stop(v);
|
||||
+
|
||||
+ list_for_each_entry(not, &v->notify, list) {
|
||||
+ not->stop(tclimit);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ v->__start = (unsigned long)sw_start_addr;
|
||||
+
|
||||
+ if (!vpe_run(v)) {
|
||||
+ pr_debug("VPE loader: VPE1 running successfully\n");
|
||||
+ return 0;
|
||||
+ }
|
||||
+ return -1;
|
||||
+}
|
||||
+EXPORT_SYMBOL(vpe1_sw_start);
|
||||
+
|
||||
+int32_t vpe1_sw_stop(uint32_t flags)
|
||||
+{
|
||||
+ struct vpe *v = get_vpe(tclimit);
|
||||
+
|
||||
+ if (!vpe_free(v)) {
|
||||
+ pr_debug("RP Stopped\n");
|
||||
+ return 0;
|
||||
+ } else
|
||||
+ return -1;
|
||||
+}
|
||||
+EXPORT_SYMBOL(vpe1_sw_stop);
|
||||
+#endif
|
||||
--- a/arch/mips/kernel/vpe.c
|
||||
+++ b/arch/mips/kernel/vpe.c
|
||||
@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = {
|
||||
.tc_list = LIST_HEAD_INIT(vpecontrol.tc_list)
|
||||
};
|
||||
|
||||
+#ifdef CONFIG_IFX_VPE_EXT
|
||||
+unsigned int vpe1_load_addr;
|
||||
+
|
||||
+static int __init load_address(char *str)
|
||||
+{
|
||||
+ get_option(&str, &vpe1_load_addr);
|
||||
+ return 1;
|
||||
+}
|
||||
+__setup("vpe1_load_addr=", load_address);
|
||||
+
|
||||
+static unsigned int vpe1_mem;
|
||||
+static int __init vpe1mem(char *str)
|
||||
+{
|
||||
+ vpe1_mem = memparse(str, &str);
|
||||
+ return 1;
|
||||
+}
|
||||
+__setup("vpe1_mem=", vpe1mem);
|
||||
+
|
||||
+uint32_t vpe1_get_load_addr(uint32_t flags)
|
||||
+{
|
||||
+ return vpe1_load_addr;
|
||||
+}
|
||||
+EXPORT_SYMBOL(vpe1_get_load_addr);
|
||||
+
|
||||
+uint32_t vpe1_get_max_mem(uint32_t flags)
|
||||
+{
|
||||
+ if (!vpe1_mem)
|
||||
+ return P_SIZE;
|
||||
+ else
|
||||
+ return vpe1_mem;
|
||||
+}
|
||||
+EXPORT_SYMBOL(vpe1_get_max_mem);
|
||||
+
|
||||
+#endif
|
||||
+
|
||||
/* get the vpe associated with this minor */
|
||||
struct vpe *get_vpe(int minor)
|
||||
{
|
||||
--- a/arch/mips/lantiq/prom.c
|
||||
+++ b/arch/mips/lantiq/prom.c
|
||||
@@ -31,10 +31,14 @@ EXPORT_SYMBOL_GPL(ebu_lock);
|
||||
*/
|
||||
static struct ltq_soc_info soc_info;
|
||||
|
||||
+/* for Multithreading (APRP), vpe.c will use it */
|
||||
+unsigned long cp0_memsize;
|
||||
+
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return soc_info.sys_type;
|
||||
}
|
||||
+EXPORT_SYMBOL(ltq_soc_type);
|
||||
|
||||
int ltq_soc_type(void)
|
||||
{
|
||||
--- a/arch/mips/include/asm/mipsmtregs.h
|
||||
+++ b/arch/mips/include/asm/mipsmtregs.h
|
||||
@@ -31,6 +31,9 @@
|
||||
#define read_c0_vpeconf1() __read_32bit_c0_register($1, 3)
|
||||
#define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val)
|
||||
|
||||
+#define read_c0_vpeopt() __read_32bit_c0_register($1, 7)
|
||||
+#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val)
|
||||
+
|
||||
#define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
|
||||
#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
|
||||
|
||||
@@ -376,6 +379,8 @@ do { \
|
||||
#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
|
||||
#define read_vpe_c0_vpeconf1() mftc0(1, 3)
|
||||
#define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val)
|
||||
+#define read_vpe_c0_vpeopt() mftc0(1, 7)
|
||||
+#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val)
|
||||
#define read_vpe_c0_count() mftc0(9, 0)
|
||||
#define write_vpe_c0_count(val) mttc0(9, 0, val)
|
||||
#define read_vpe_c0_status() mftc0(12, 0)
|
||||
@ -1,22 +0,0 @@ |
||||
--- a/arch/mips/pci/pci-lantiq.c
|
||||
+++ b/arch/mips/pci/pci-lantiq.c
|
||||
@@ -62,6 +62,8 @@
|
||||
#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
|
||||
#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
|
||||
|
||||
+extern u32 max_low_pfn;
|
||||
+
|
||||
__iomem void *ltq_pci_mapped_cfg;
|
||||
static __iomem void *ltq_pci_membase;
|
||||
|
||||
@@ -87,8 +89,8 @@ static inline u32 ltq_calc_bar11mask(voi
|
||||
u32 mem, bar11mask;
|
||||
|
||||
/* BAR11MASK value depends on available memory on system. */
|
||||
- mem = get_num_physpages() * PAGE_SIZE;
|
||||
- bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
|
||||
+ mem = max_low_pfn << PAGE_SHIFT;
|
||||
+ bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8;
|
||||
|
||||
return bar11mask;
|
||||
}
|
||||
@ -1,14 +0,0 @@ |
||||
--- a/arch/mips/kernel/vpe-mt.c
|
||||
+++ b/arch/mips/kernel/vpe-mt.c
|
||||
@@ -132,7 +132,10 @@ int vpe_run(struct vpe *v)
|
||||
* kernels need to turn it on, even if that wasn't the pre-dvpe() state.
|
||||
*/
|
||||
#ifdef CONFIG_SMP
|
||||
- evpe(vpeflags);
|
||||
+ if (!setup_max_cpus) /* nosmp is set */
|
||||
+ evpe(EVPE_ENABLE);
|
||||
+ else
|
||||
+ evpe(vpeflags);
|
||||
#else
|
||||
evpe(EVPE_ENABLE);
|
||||
#endif
|
||||
@ -1,222 +0,0 @@ |
||||
--- a/drivers/mtd/maps/lantiq-flash.c
|
||||
+++ b/drivers/mtd/maps/lantiq-flash.c
|
||||
@@ -19,6 +19,7 @@
|
||||
#include <linux/mtd/cfi.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
+#include <linux/mtd/concat.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
@@ -38,13 +39,16 @@ enum {
|
||||
LTQ_NOR_NORMAL
|
||||
};
|
||||
|
||||
+#define MAX_RESOURCES 4
|
||||
+
|
||||
struct ltq_mtd {
|
||||
- struct resource *res;
|
||||
- struct mtd_info *mtd;
|
||||
- struct map_info *map;
|
||||
+ struct mtd_info *mtd[MAX_RESOURCES];
|
||||
+ struct mtd_info *cmtd;
|
||||
+ struct map_info map[MAX_RESOURCES];
|
||||
};
|
||||
|
||||
static const char ltq_map_name[] = "ltq_nor";
|
||||
+static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL };
|
||||
|
||||
static map_word
|
||||
ltq_read16(struct map_info *map, unsigned long adr)
|
||||
@@ -108,12 +112,44 @@ ltq_copy_to(struct map_info *map, unsign
|
||||
}
|
||||
|
||||
static int
|
||||
+ltq_mtd_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);
|
||||
+ int i;
|
||||
+
|
||||
+ if (ltq_mtd == NULL)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (ltq_mtd->cmtd) {
|
||||
+ mtd_device_unregister(ltq_mtd->cmtd);
|
||||
+ if (ltq_mtd->cmtd != ltq_mtd->mtd[0])
|
||||
+ mtd_concat_destroy(ltq_mtd->cmtd);
|
||||
+ }
|
||||
+
|
||||
+ for (i = 0; i < MAX_RESOURCES; i++) {
|
||||
+ if (ltq_mtd->mtd[i] != NULL)
|
||||
+ map_destroy(ltq_mtd->mtd[i]);
|
||||
+ }
|
||||
+
|
||||
+ kfree(ltq_mtd);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
ltq_mtd_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct mtd_part_parser_data ppdata;
|
||||
struct ltq_mtd *ltq_mtd;
|
||||
struct cfi_private *cfi;
|
||||
- int err;
|
||||
+ int err = 0;
|
||||
+ int i;
|
||||
+ int devices_found = 0;
|
||||
+
|
||||
+ static const char *rom_probe_types[] = {
|
||||
+ "cfi_probe", "jedec_probe", NULL
|
||||
+ };
|
||||
+ const char **type;
|
||||
|
||||
if (of_machine_is_compatible("lantiq,falcon") &&
|
||||
(ltq_boot_select() != BS_FLASH)) {
|
||||
@@ -127,75 +163,90 @@ ltq_mtd_probe(struct platform_device *pd
|
||||
|
||||
platform_set_drvdata(pdev, ltq_mtd);
|
||||
|
||||
- ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
- if (!ltq_mtd->res) {
|
||||
- dev_err(&pdev->dev, "failed to get memory resource\n");
|
||||
- return -ENOENT;
|
||||
+ for (i = 0; i < pdev->num_resources; i++) {
|
||||
+ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n",
|
||||
+ (unsigned long long)resource_size(&pdev->resource[i]),
|
||||
+ (unsigned long long)pdev->resource[i].start);
|
||||
+
|
||||
+ if (!devm_request_mem_region(&pdev->dev,
|
||||
+ pdev->resource[i].start,
|
||||
+ resource_size(&pdev->resource[i]),
|
||||
+ dev_name(&pdev->dev))) {
|
||||
+ dev_err(&pdev->dev, "Could not reserve memory region\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ ltq_mtd->map[i].name = ltq_map_name;
|
||||
+ ltq_mtd->map[i].bankwidth = 2;
|
||||
+ ltq_mtd->map[i].read = ltq_read16;
|
||||
+ ltq_mtd->map[i].write = ltq_write16;
|
||||
+ ltq_mtd->map[i].copy_from = ltq_copy_from;
|
||||
+ ltq_mtd->map[i].copy_to = ltq_copy_to;
|
||||
+
|
||||
+ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
|
||||
+ ltq_mtd->map[i].phys = NO_XIP;
|
||||
+ else
|
||||
+ ltq_mtd->map[i].phys = pdev->resource[i].start;
|
||||
+ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]);
|
||||
+ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start,
|
||||
+ ltq_mtd->map[i].size);
|
||||
+ if (IS_ERR(ltq_mtd->map[i].virt))
|
||||
+ return PTR_ERR(ltq_mtd->map[i].virt);
|
||||
+
|
||||
+ if (ltq_mtd->map[i].virt == NULL) {
|
||||
+ dev_err(&pdev->dev, "Failed to ioremap flash region\n");
|
||||
+ err = PTR_ERR(ltq_mtd->map[i].virt);
|
||||
+ goto err_out;
|
||||
+ }
|
||||
+
|
||||
+ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING;
|
||||
+ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++)
|
||||
+ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]);
|
||||
+ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL;
|
||||
+
|
||||
+ if (!ltq_mtd->mtd[i]) {
|
||||
+ dev_err(&pdev->dev, "probing failed\n");
|
||||
+ return -ENXIO;
|
||||
+ } else {
|
||||
+ devices_found++;
|
||||
+ }
|
||||
+
|
||||
+ ltq_mtd->mtd[i]->owner = THIS_MODULE;
|
||||
+ ltq_mtd->mtd[i]->dev.parent = &pdev->dev;
|
||||
+
|
||||
+ cfi = ltq_mtd->map[i].fldrv_priv;
|
||||
+ cfi->addr_unlock1 ^= 1;
|
||||
+ cfi->addr_unlock2 ^= 1;
|
||||
}
|
||||
|
||||
- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info),
|
||||
- GFP_KERNEL);
|
||||
- if (!ltq_mtd->map)
|
||||
- return -ENOMEM;
|
||||
+ if (devices_found == 1) {
|
||||
+ ltq_mtd->cmtd = ltq_mtd->mtd[0];
|
||||
+ } else if (devices_found > 1) {
|
||||
+ /*
|
||||
+ * We detected multiple devices. Concatenate them together.
|
||||
+ */
|
||||
+ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev));
|
||||
+ if (ltq_mtd->cmtd == NULL)
|
||||
+ err = -ENXIO;
|
||||
+ }
|
||||
|
||||
- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
|
||||
- ltq_mtd->map->phys = NO_XIP;
|
||||
- else
|
||||
- ltq_mtd->map->phys = ltq_mtd->res->start;
|
||||
- ltq_mtd->res->start;
|
||||
- ltq_mtd->map->size = resource_size(ltq_mtd->res);
|
||||
- ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res);
|
||||
- if (IS_ERR(ltq_mtd->map->virt))
|
||||
- return PTR_ERR(ltq_mtd->map->virt);
|
||||
-
|
||||
- ltq_mtd->map->name = ltq_map_name;
|
||||
- ltq_mtd->map->bankwidth = 2;
|
||||
- ltq_mtd->map->read = ltq_read16;
|
||||
- ltq_mtd->map->write = ltq_write16;
|
||||
- ltq_mtd->map->copy_from = ltq_copy_from;
|
||||
- ltq_mtd->map->copy_to = ltq_copy_to;
|
||||
-
|
||||
- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING;
|
||||
- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map);
|
||||
- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL;
|
||||
-
|
||||
- if (!ltq_mtd->mtd) {
|
||||
- dev_err(&pdev->dev, "probing failed\n");
|
||||
- return -ENXIO;
|
||||
- }
|
||||
-
|
||||
- ltq_mtd->mtd->dev.parent = &pdev->dev;
|
||||
-
|
||||
- cfi = ltq_mtd->map->fldrv_priv;
|
||||
- cfi->addr_unlock1 ^= 1;
|
||||
- cfi->addr_unlock2 ^= 1;
|
||||
+ ltq_mtd->cmtd->dev.parent = &pdev->dev;
|
||||
|
||||
ppdata.of_node = pdev->dev.of_node;
|
||||
- err = mtd_device_parse_register(ltq_mtd->mtd, NULL, &ppdata, NULL, 0);
|
||||
+ err = mtd_device_parse_register(ltq_mtd->cmtd, ltq_probe_types,
|
||||
+ &ppdata, NULL, 0);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "failed to add partitions\n");
|
||||
- goto err_destroy;
|
||||
+ goto err_out;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
-err_destroy:
|
||||
- map_destroy(ltq_mtd->mtd);
|
||||
+err_out:
|
||||
+ ltq_mtd_remove(pdev);
|
||||
return err;
|
||||
}
|
||||
|
||||
-static int
|
||||
-ltq_mtd_remove(struct platform_device *pdev)
|
||||
-{
|
||||
- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);
|
||||
-
|
||||
- if (ltq_mtd && ltq_mtd->mtd) {
|
||||
- mtd_device_unregister(ltq_mtd->mtd);
|
||||
- map_destroy(ltq_mtd->mtd);
|
||||
- }
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
static const struct of_device_id ltq_mtd_match[] = {
|
||||
{ .compatible = "lantiq,nor" },
|
||||
{},
|
||||
@ -1,152 +0,0 @@ |
||||
From 58078a30038b578c26c532545448fe3746648390 Mon Sep 17 00:00:00 2001
|
||||
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Date: Thu, 29 Dec 2016 21:02:57 +0100
|
||||
Subject: [PATCH] MIPS: lantiq: lock DMA register accesses for SMP
|
||||
|
||||
The DMA controller channel and port configuration is changed by
|
||||
selecting the port or channel in one register and then update the
|
||||
configuration in other registers. This has to be done in an atomic
|
||||
operation. Previously only the local interrupts were deactivated which
|
||||
works for single CPU systems. If the system supports SMP a better
|
||||
locking is needed, use spinlocks instead.
|
||||
On more recent SoCs (at least xrx200 and later) there are two memory
|
||||
regions to change the configuration, there we could use one area for
|
||||
each CPU and do not have to synchronize between the CPUs and more.
|
||||
|
||||
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
---
|
||||
arch/mips/lantiq/xway/dma.c | 38 ++++++++++++++++++++------------------
|
||||
1 file changed, 20 insertions(+), 18 deletions(-)
|
||||
|
||||
--- a/arch/mips/lantiq/xway/dma.c
|
||||
+++ b/arch/mips/lantiq/xway/dma.c
|
||||
@@ -20,6 +20,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/module.h>
|
||||
+#include <linux/spinlock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
@@ -59,16 +60,17 @@
|
||||
ltq_dma_membase + (z))
|
||||
|
||||
static void __iomem *ltq_dma_membase;
|
||||
+static DEFINE_SPINLOCK(ltq_dma_lock);
|
||||
|
||||
void
|
||||
ltq_dma_enable_irq(struct ltq_dma_channel *ch)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
- local_irq_save(flags);
|
||||
+ spin_lock_irqsave(<q_dma_lock, flags);
|
||||
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
|
||||
ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
|
||||
- local_irq_restore(flags);
|
||||
+ spin_unlock_irqrestore(<q_dma_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
|
||||
|
||||
@@ -77,10 +79,10 @@ ltq_dma_disable_irq(struct ltq_dma_chann
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
- local_irq_save(flags);
|
||||
+ spin_lock_irqsave(<q_dma_lock, flags);
|
||||
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
|
||||
ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
|
||||
- local_irq_restore(flags);
|
||||
+ spin_unlock_irqrestore(<q_dma_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
|
||||
|
||||
@@ -89,10 +91,10 @@ ltq_dma_ack_irq(struct ltq_dma_channel *
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
- local_irq_save(flags);
|
||||
+ spin_lock_irqsave(<q_dma_lock, flags);
|
||||
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
|
||||
ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
|
||||
- local_irq_restore(flags);
|
||||
+ spin_unlock_irqrestore(<q_dma_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
|
||||
|
||||
@@ -101,11 +103,11 @@ ltq_dma_open(struct ltq_dma_channel *ch)
|
||||
{
|
||||
unsigned long flag;
|
||||
|
||||
- local_irq_save(flag);
|
||||
+ spin_lock_irqsave(<q_dma_lock, flag);
|
||||
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
|
||||
ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
|
||||
- ltq_dma_enable_irq(ch);
|
||||
- local_irq_restore(flag);
|
||||
+ ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
|
||||
+ spin_unlock_irqrestore(<q_dma_lock, flag);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ltq_dma_open);
|
||||
|
||||
@@ -114,11 +116,11 @@ ltq_dma_close(struct ltq_dma_channel *ch
|
||||
{
|
||||
unsigned long flag;
|
||||
|
||||
- local_irq_save(flag);
|
||||
+ spin_lock_irqsave(<q_dma_lock, flag);
|
||||
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
|
||||
ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
|
||||
- ltq_dma_disable_irq(ch);
|
||||
- local_irq_restore(flag);
|
||||
+ ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
|
||||
+ spin_unlock_irqrestore(<q_dma_lock, flag);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ltq_dma_close);
|
||||
|
||||
@@ -133,7 +135,7 @@ ltq_dma_alloc(struct ltq_dma_channel *ch
|
||||
&ch->phys, GFP_ATOMIC);
|
||||
memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE);
|
||||
|
||||
- local_irq_save(flags);
|
||||
+ spin_lock_irqsave(<q_dma_lock, flags);
|
||||
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
|
||||
ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
|
||||
ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
|
||||
@@ -142,7 +144,7 @@ ltq_dma_alloc(struct ltq_dma_channel *ch
|
||||
ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
|
||||
while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
|
||||
;
|
||||
- local_irq_restore(flags);
|
||||
+ spin_unlock_irqrestore(<q_dma_lock, flags);
|
||||
}
|
||||
|
||||
void
|
||||
@@ -152,11 +154,11 @@ ltq_dma_alloc_tx(struct ltq_dma_channel
|
||||
|
||||
ltq_dma_alloc(ch);
|
||||
|
||||
- local_irq_save(flags);
|
||||
+ spin_lock_irqsave(<q_dma_lock, flags);
|
||||
ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
|
||||
ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
|
||||
ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
|
||||
- local_irq_restore(flags);
|
||||
+ spin_unlock_irqrestore(<q_dma_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
|
||||
|
||||
@@ -167,11 +169,11 @@ ltq_dma_alloc_rx(struct ltq_dma_channel
|
||||
|
||||
ltq_dma_alloc(ch);
|
||||
|
||||
- local_irq_save(flags);
|
||||
+ spin_lock_irqsave(<q_dma_lock, flags);
|
||||
ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
|
||||
ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
|
||||
ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
|
||||
- local_irq_restore(flags);
|
||||
+ spin_unlock_irqrestore(<q_dma_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
|
||||
|
||||
@ -1,11 +0,0 @@ |
||||
--- a/drivers/mtd/chips/cfi_cmdset_0001.c
|
||||
+++ b/drivers/mtd/chips/cfi_cmdset_0001.c
|
||||
@@ -39,7 +39,7 @@
|
||||
/* #define CMDSET0001_DISABLE_WRITE_SUSPEND */
|
||||
|
||||
// debugging, turns off buffer write mode if set to 1
|
||||
-#define FORCE_WORD_WRITE 0
|
||||
+#define FORCE_WORD_WRITE 1
|
||||
|
||||
/* Intel chips */
|
||||
#define I82802AB 0x00ad
|
||||
@ -1,30 +0,0 @@ |
||||
--- a/arch/mips/lantiq/xway/sysctrl.c
|
||||
+++ b/arch/mips/lantiq/xway/sysctrl.c
|
||||
@@ -442,6 +442,20 @@ static void clkdev_add_clkout(void)
|
||||
}
|
||||
}
|
||||
|
||||
+static void set_phy_clock_source(struct device_node *np_cgu)
|
||||
+{
|
||||
+ u32 phy_clk_src, ifcc;
|
||||
+
|
||||
+ if (!np_cgu)
|
||||
+ return;
|
||||
+
|
||||
+ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
|
||||
+ return;
|
||||
+
|
||||
+ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
|
||||
+ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
|
||||
+}
|
||||
+
|
||||
/* bring up all register ranges that we need for basic system control */
|
||||
void __init ltq_soc_init(void)
|
||||
{
|
||||
@@ -628,4 +642,6 @@ void __init ltq_soc_init(void)
|
||||
if (of_machine_is_compatible("lantiq,vr9"))
|
||||
xbar_fpi_burst_disable();
|
||||
usb_set_clock();
|
||||
+
|
||||
+ set_phy_clock_source(np_cgu);
|
||||
}
|
||||
@ -1,184 +0,0 @@ |
||||
--- a/drivers/hwmon/Makefile
|
||||
+++ b/drivers/hwmon/Makefile
|
||||
@@ -107,6 +107,7 @@ obj-$(CONFIG_SENSORS_LTC4222) += ltc4222
|
||||
obj-$(CONFIG_SENSORS_LTC4245) += ltc4245.o
|
||||
obj-$(CONFIG_SENSORS_LTC4260) += ltc4260.o
|
||||
obj-$(CONFIG_SENSORS_LTC4261) += ltc4261.o
|
||||
+obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) += ltq-cputemp.o
|
||||
obj-$(CONFIG_SENSORS_MAX1111) += max1111.o
|
||||
obj-$(CONFIG_SENSORS_MAX16065) += max16065.o
|
||||
obj-$(CONFIG_SENSORS_MAX1619) += max1619.o
|
||||
--- a/drivers/hwmon/Kconfig
|
||||
+++ b/drivers/hwmon/Kconfig
|
||||
@@ -753,6 +753,14 @@ config SENSORS_LTC4261
|
||||
This driver can also be built as a module. If so, the module will
|
||||
be called ltc4261.
|
||||
|
||||
+config SENSORS_LTQ_CPUTEMP
|
||||
+ bool "Lantiq CPU temperature sensor"
|
||||
+ depends on LANTIQ
|
||||
+ default n
|
||||
+ help
|
||||
+ If you say yes here you get support for the temperature
|
||||
+ sensor inside your CPU.
|
||||
+
|
||||
config SENSORS_MAX1111
|
||||
tristate "Maxim MAX1111 Serial 8-bit ADC chip and compatibles"
|
||||
depends on SPI_MASTER
|
||||
--- /dev/null
|
||||
+++ b/drivers/hwmon/ltq-cputemp.c
|
||||
@@ -0,0 +1,154 @@
|
||||
+/* Lantiq CPU Temperatur sensor driver for xrx200
|
||||
+ *
|
||||
+ * Copyright (C) 2016 Florian Eckert <feckert@tdt.de>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License as published by
|
||||
+ * the Free Software Foundation; either version 2 of the License, or
|
||||
+ * (at your option) any later version
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details
|
||||
+ *
|
||||
+ * You should have received a copy of the GNU General Public License
|
||||
+ * along with this program; if not, see <http://www.gnu.org/licenses/>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/hwmon.h>
|
||||
+#include <linux/hwmon-sysfs.h>
|
||||
+
|
||||
+#include <lantiq_soc.h>
|
||||
+
|
||||
+/* gphy1 configuration register contains cpu temperature */
|
||||
+#define CGU_GPHY1_CR 0x0040
|
||||
+#define CGU_TEMP_PD BIT(19)
|
||||
+
|
||||
+static void ltq_cputemp_enable(void)
|
||||
+{
|
||||
+ ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR);
|
||||
+
|
||||
+ /* wait a short moment to let the SoC get the first temperatur value */
|
||||
+ mdelay(100);
|
||||
+}
|
||||
+
|
||||
+static void ltq_cputemp_disable(void)
|
||||
+{
|
||||
+ ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR);
|
||||
+}
|
||||
+
|
||||
+static int ltq_cputemp_read(void)
|
||||
+{
|
||||
+ int value;
|
||||
+
|
||||
+ /* get the temperature including one decimal place */
|
||||
+ value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF;
|
||||
+ value = (value << 2 ) + value;
|
||||
+
|
||||
+ /* range -38 to +154 °C, register value zero is -38.0 °C */
|
||||
+ value -= 380;
|
||||
+
|
||||
+ return value;
|
||||
+}
|
||||
+
|
||||
+static ssize_t show_cputemp(struct device *dev,
|
||||
+ struct device_attribute *attr, char *buf)
|
||||
+{
|
||||
+ int value;
|
||||
+
|
||||
+ value = ltq_cputemp_read();
|
||||
+ /* scale temp to millidegree */
|
||||
+ value = value * 100;
|
||||
+
|
||||
+ return sprintf(buf, "%d\n", value);
|
||||
+}
|
||||
+
|
||||
+static DEVICE_ATTR(temp1_input, S_IRUGO, show_cputemp, NULL);
|
||||
+
|
||||
+static struct attribute *ltq_cputemp_attrs[] = {
|
||||
+ &dev_attr_temp1_input.attr,
|
||||
+ NULL
|
||||
+};
|
||||
+
|
||||
+ATTRIBUTE_GROUPS(ltq_cputemp);
|
||||
+
|
||||
+static int ltq_cputemp_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ int value = 0;
|
||||
+ int ret;
|
||||
+ struct device *hwmon_dev;
|
||||
+
|
||||
+ /* available on vr9 v1.2 SoCs only */
|
||||
+ if (ltq_soc_type() != SOC_TYPE_VR9_2)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ hwmon_dev = devm_hwmon_device_register_with_groups(&pdev->dev,
|
||||
+ "CPU0",
|
||||
+ NULL,
|
||||
+ ltq_cputemp_groups);
|
||||
+
|
||||
+ if (IS_ERR(hwmon_dev)) {
|
||||
+ dev_err(&pdev->dev, "Failed to register as hwmon device");
|
||||
+ ret = PTR_ERR(hwmon_dev);
|
||||
+ goto error_hwmon;
|
||||
+ }
|
||||
+
|
||||
+ ltq_cputemp_enable();
|
||||
+ value = ltq_cputemp_read();
|
||||
+ dev_info(&pdev->dev, "Current CPU die temperature: %d.%d °C", value / 10, value % 10);
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+error_hwmon:
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int ltq_cputemp_release(struct platform_device *pdev)
|
||||
+{
|
||||
+ hwmon_device_unregister(&pdev->dev);
|
||||
+ ltq_cputemp_disable();
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+const struct of_device_id ltq_cputemp_match[] = {
|
||||
+ { .compatible = "lantiq,cputemp" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, ltq_cputemp_match);
|
||||
+
|
||||
+static struct platform_driver ltq_cputemp_driver = {
|
||||
+ .probe = ltq_cputemp_probe,
|
||||
+ .remove = ltq_cputemp_release,
|
||||
+ .driver = {
|
||||
+ .name = "ltq-cputemp",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = ltq_cputemp_match,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+int __init init_ltq_cputemp(void)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = platform_driver_register(<q_cputemp_driver);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+void clean_ltq_cputemp(void)
|
||||
+{
|
||||
+ platform_driver_unregister(<q_cputemp_driver);
|
||||
+ return;
|
||||
+}
|
||||
+
|
||||
+module_init(init_ltq_cputemp);
|
||||
+module_exit(clean_ltq_cputemp);
|
||||
+
|
||||
+MODULE_AUTHOR("Florian Eckert <feckert@tdt.de>");
|
||||
+
|
||||
+MODULE_DESCRIPTION("Lantiq Temperature Sensor");
|
||||
+MODULE_LICENSE("GPL");
|
||||
@ -1,49 +0,0 @@ |
||||
From 15f37e1588920e010f20b53f04af94e91b8ee714 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jogo@openwrt.org>
|
||||
Date: Mon, 20 Jun 2016 11:27:37 +0200
|
||||
Subject: [PATCH] MIPS: store the appended dtb address in a variable
|
||||
|
||||
Instead of rewriting the arguments to match the UHI spec, store the
|
||||
address of a appended or UHI supplied dtb in fw_supplied_dtb.
|
||||
|
||||
That way the original bootloader arugments are kept intact while still
|
||||
making the use of an appended dtb invisible for mach code.
|
||||
|
||||
Mach code can still find out if it is an appended dtb by comparing
|
||||
fw_arg1 with fw_supplied_dtb.
|
||||
|
||||
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
||||
Cc: Kevin Cernekee <cernekee@gmail.com>
|
||||
Cc: Florian Fainelli <f.fainelli@gmail.com>
|
||||
Cc: John Crispin <john@phrozen.org>
|
||||
Cc: Paul Burton <paul.burton@imgtec.com>
|
||||
Cc: James Hogan <james.hogan@imgtec.com>
|
||||
Cc: Alban Bedel <albeu@free.fr>
|
||||
Cc: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
|
||||
Cc: Antony Pavlov <antonynpavlov@gmail.com>
|
||||
Cc: linux-mips@linux-mips.org
|
||||
Patchwork: https://patchwork.linux-mips.org/patch/13699/
|
||||
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
||||
---
|
||||
arch/mips/ath79/setup.c | 4 ++--
|
||||
arch/mips/bmips/setup.c | 4 ++--
|
||||
arch/mips/include/asm/bootinfo.h | 4 ++++
|
||||
arch/mips/kernel/head.S | 21 ++++++++++++++-------
|
||||
arch/mips/kernel/setup.c | 4 ++++
|
||||
arch/mips/lantiq/prom.c | 4 ++--
|
||||
arch/mips/pic32/pic32mzda/init.c | 4 ++--
|
||||
7 files changed, 30 insertions(+), 15 deletions(-)
|
||||
|
||||
--- a/arch/mips/lantiq/prom.c
|
||||
+++ b/arch/mips/lantiq/prom.c
|
||||
@@ -78,8 +78,8 @@ void __init plat_mem_setup(void)
|
||||
|
||||
set_io_port_base((unsigned long) KSEG1);
|
||||
|
||||
- if (fw_arg0 == -2) /* UHI interface */
|
||||
- dtb = (void *)fw_arg1;
|
||||
+ if (fw_passed_dtb) /* UHI interface */
|
||||
+ dtb = (void *)fw_passed_dtb;
|
||||
else if (__dtb_start != __dtb_end)
|
||||
dtb = (void *)__dtb_start;
|
||||
else
|
||||
Loading…
Reference in new issue