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@ -93,13 +93,13 @@ static int mcs8140_pci_host_status(void) |
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{ |
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u32 host_status; |
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host_status = __raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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host_status = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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if (host_status & PCI_FATAL_ERROR) { |
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__raw_writel(host_status & 0xfffffff0, |
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writel_relaxed(host_status & 0xfffffff0, |
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mcs8140_pci_master_base + PCI_IF_CONFIG); |
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/* flush write */ |
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host_status = |
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__raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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return 1; |
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} |
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@ -124,7 +124,7 @@ static int mcs8140_pci_read_config(struct pci_bus *bus, |
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break; |
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default: |
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addr &= ~3; |
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v = __raw_readl(addr); |
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v = readl_relaxed(addr); |
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break; |
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} |
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} else |
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@ -140,10 +140,10 @@ static int mcs8140_pci_read_config(struct pci_bus *bus, |
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static void mcs8140_eeprom_emu_init(void) |
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{ |
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__raw_writel(0x0000000F, mcs8140_eeprom_emu_base + EPRM_SDRAM_FUNC0); |
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__raw_writel(0x08000000, MCS8140_PCI_CFG_VIRT_BASE + 0x10); |
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writel_relaxed(0x0000000F, mcs8140_eeprom_emu_base + EPRM_SDRAM_FUNC0); |
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writel_relaxed(0x08000000, MCS8140_PCI_CFG_VIRT_BASE + 0x10); |
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/* Set the DONE bit of the EEPROM emulator */ |
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__raw_writel(0x01, mcs8140_eeprom_emu_base + EPRM_DONE); |
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writel_relaxed(0x01, mcs8140_eeprom_emu_base + EPRM_DONE); |
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} |
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static int mcs8140_pci_write_config(struct pci_bus *bus, |
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@ -161,7 +161,7 @@ static int mcs8140_pci_write_config(struct pci_bus *bus, |
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__raw_writew((u16)val, addr); |
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break; |
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case 4: |
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__raw_writel(val, addr); |
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writel_relaxed(val, addr); |
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break; |
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} |
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} |
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@ -260,7 +260,7 @@ int __init pci_mcs8140_setup(int nr, struct pci_sys_data *sys) |
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goto out; |
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} |
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val = __raw_readl(MCS8140_PCI_CFG_VIRT_BASE); |
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val = readl_relaxed(MCS8140_PCI_CFG_VIRT_BASE); |
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if (val != MCS8140_PCI_DEVICE_ID) { |
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pr_err("cannot find MCS8140 PCI Core: %08x\n", val); |
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ret = -EIO; |
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@ -269,11 +269,11 @@ int __init pci_mcs8140_setup(int nr, struct pci_sys_data *sys) |
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pr_info("MCS8140 PCI core found\n"); |
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val = __raw_readl(MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND); |
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val = readl_relaxed(MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND); |
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/* Added to support wireless cards */ |
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__raw_writel(0, MCS8140_PCI_CFG_VIRT_BASE + 0x40); |
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__raw_writel(val | 0x147, MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND); |
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val = __raw_readl(MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND); |
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writel_relaxed(0, MCS8140_PCI_CFG_VIRT_BASE + 0x40); |
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writel_relaxed(val | 0x147, MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND); |
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val = readl_relaxed(MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND); |
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ret = 1; |
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out: |
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return ret; |
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@ -302,14 +302,14 @@ static irqreturn_t mcs8140_pci_abort_interrupt(int irq, void *dummy) |
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{ |
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u32 word; |
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word = __raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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if (!(word & (1 << 24))) |
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return IRQ_NONE; |
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__raw_writel(word & 0xfffffff0, |
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writel_relaxed(word & 0xfffffff0, |
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mcs8140_pci_master_base + PCI_IF_CONFIG); |
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/* flush write */ |
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word = __raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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return IRQ_HANDLED; |
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} |
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@ -319,12 +319,12 @@ static int mcs8140_pci_abort_irq_init(int irq) |
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u32 word; |
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/* Enable Interrupt in PCI Master Core */ |
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word = __raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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word |= (1 << 24); |
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__raw_writel(word, mcs8140_pci_master_base + PCI_IF_CONFIG); |
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writel_relaxed(word, mcs8140_pci_master_base + PCI_IF_CONFIG); |
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/* flush write */ |
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word = __raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG); |
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return request_irq(irq, mcs8140_pci_abort_interrupt, 0, |
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"PCI abort", NULL); |
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