SVN-Revision: 26352
@ -273,8 +273,8 @@
+#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
+
+/*------------ WDT */
+#define LQ_WDT_BASE 0x1F880000
+#define LQ_WDT_SIZE 0x400
+#define LQ_WDT_BASE 0x1F8803F0
+#define LQ_WDT_SIZE 0x10
+/*------------ Serial To Parallel conversion */
+#define LQ_STP_BASE 0x1E100BB0
@ -49,8 +49,8 @@
+#define LQ_WDT_PW1 0x00BE0000
+#define LQ_WDT_PW2 0x00DC0000
+#define LQ_BIU_WDT_CR 0x3F0
+#define LQ_BIU_WDT_SR 0x3F8
+#define LQ_BIU_WDT_CR 0x0
+#define LQ_BIU_WDT_SR 0x8
+#ifndef CONFIG_WATCHDOG_NOWAYOUT
+static int wdt_ok_to_close;