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@ -1,4 +1,20 @@ |
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bgmac: add supprot for BCM4707
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From 2e3759f95d3c96282c19e6f57274d816c6cf1a0e Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 10 Nov 2013 21:13:20 +0100
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Subject: [PATCH 4/5] bgmac: reset all cores on Northstar SoC
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On the Northstar SoC (BCM4707 and BCM53018) we have to enable all GMAC
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cores when we just want to use on. We iterate over all the cores and
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activate them.
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Subject: [PATCH 5/5] bgmac: add support for Northstar SoC (BCM4707, BCM53018)
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This adds support for the Northstar SoC. This SoC does not have a PMU in
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bcma and no register on it should be called. In addition it support 2.5
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GBit/s Ethernet to the PHY.
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This GMAC core is not fully working there are still problems with the
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DMA controller.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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@ -14,7 +30,7 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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default:
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bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
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}
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@@ -837,12 +840,25 @@ static void bgmac_mac_speed(struct bgmac
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@@ -837,12 +840,26 @@ static void bgmac_mac_speed(struct bgmac
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static void bgmac_miiconfig(struct bgmac *bgmac)
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{
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@ -29,13 +45,14 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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+ if (ci->id == BCMA_CHIP_ID_BCM4707 ||
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+ ci->id == BCMA_CHIP_ID_BCM53018) {
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+ bcma_awrite32(core, BCMA_IOCTL,
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+ bcma_aread32(core, BCMA_IOCTL) | 0x44);
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+ bcma_aread32(core, BCMA_IOCTL) | 0x40 |
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+ BGMAC_BCMA_IOCTL_SW_CLKEN);
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+ bgmac->mac_speed = SPEED_2500;
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bgmac->mac_duplex = DUPLEX_FULL;
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bgmac_mac_speed(bgmac);
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+ } else {
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+ imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
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+ BGMAC_DS_MM_SHIFT;
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+ imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
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+ BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
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+ if (imode == 0 || imode == 1) {
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+ bgmac->mac_speed = SPEED_100;
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+ bgmac->mac_duplex = DUPLEX_FULL;
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@ -44,17 +61,25 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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}
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}
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@@ -888,7 +904,8 @@ static void bgmac_chip_reset(struct bgma
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bcma_core_enable(core, flags);
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@@ -886,9 +903,14 @@ static void bgmac_chip_reset(struct bgma
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flags |= BGMAC_BCMA_IOCTL_SW_RESET;
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}
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- bcma_core_enable(core, flags);
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-
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- if (core->id.rev > 2) {
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+ if (core->id.rev > 2 && ci->id != BCMA_CHIP_ID_BCM4707 &&
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+ /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
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+ if (ci->id != BCMA_CHIP_ID_BCM4707)
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+ bcma_core_enable(core, flags);
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+
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+ /* Request Misc PLL for corerev > 2 */
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+ if (core->id.rev > 2 &&
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+ ci->id != BCMA_CHIP_ID_BCM4707 &&
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+ ci->id != BCMA_CHIP_ID_BCM53018) {
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bgmac_set(bgmac, BCMA_CLKCTLST,
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BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
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bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
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@@ -1026,12 +1043,15 @@ static void bgmac_enable(struct bgmac *b
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@@ -1026,12 +1048,16 @@ static void bgmac_enable(struct bgmac *b
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break;
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}
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@ -68,7 +93,8 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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+ ci->id != BCMA_CHIP_ID_BCM53018) {
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+ rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
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+ rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
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+ bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
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+ bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
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+ 1000000;
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+ mdp = (bp_clk * 128 / 1000) - 3;
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+ rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
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+ bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
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@ -76,32 +102,61 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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}
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/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
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@@ -1421,6 +1441,25 @@ static int bgmac_probe(struct bcma_devic
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goto err_netdev_free;
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@@ -1366,6 +1392,7 @@ static int bgmac_probe(struct bcma_devic
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struct bgmac *bgmac;
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struct ssb_sprom *sprom = &core->bus->sprom;
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u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
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+ struct bcma_chipinfo *ci = &core->bus->chipinfo;
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int err;
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/* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
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@@ -1404,8 +1431,16 @@ static int bgmac_probe(struct bcma_devic
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}
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bgmac->cmn = core->bus->drv_gmac_cmn.core;
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- bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
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- sprom->et0phyaddr;
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+ /*
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+ * Too much can go wrong in scanning MDC/MDIO playing "whos my phy?" .
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+ * Instead, explicitly use the phy address 30.
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+ */
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+ if (ci->id == BCMA_CHIP_ID_BCM4707 || ci->id == BCMA_CHIP_ID_BCM53018)
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+ bgmac->phyaddr = BGMAC_PHY_NOREGS;
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+ else
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+ bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
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+ sprom->et0phyaddr;
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+
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bgmac->phyaddr &= BGMAC_PHY_MASK;
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if (bgmac->phyaddr == BGMAC_PHY_MASK) {
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bgmac_err(bgmac, "No PHY found\n");
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@@ -1423,6 +1458,27 @@ static int bgmac_probe(struct bcma_devic
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+ /* Northstar, take all GMAC cores out of reset */
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bgmac_chip_reset(bgmac);
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+ /* For Northstar, we have to take all GMAC core out of reset */
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+ if (core->id.id == BCMA_CHIP_ID_BCM4707 ||
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+ core->id.id == BCMA_CHIP_ID_BCM53018) {
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+ struct bcma_device *ns_core;
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+ int ns_gmac;
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+
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+ /* Northstar has 4 GMAC cores */
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+ for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
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+ /* As northstar requirement, we have to reset all GAMCs before
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+ * accessing them. et_probe() call pci_enable_device() for etx
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+ * and do si_core_reset for GAMCx only. Then the other three
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+ * GAMCs didn't reset. We do it here.
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+ /* As northstar requirement, we have to reset all GAMCs
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+ * before accessing one. bgmac_chip_reset() call
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+ * bcma_core_enable() for this core. Then the other
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+ * three GAMCs didn't reset. We do it here.
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+ */
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+ ns_core = bcma_find_core_unit(core->bus, BCMA_CORE_MAC_GBIT, ns_gmac);
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+ if (!bcma_core_is_enabled(ns_core)) {
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+ ns_core = bcma_find_core_unit(core->bus,
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+ BCMA_CORE_MAC_GBIT,
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+ ns_gmac);
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+ if (ns_core && !bcma_core_is_enabled(ns_core))
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+ bcma_core_enable(ns_core, 0);
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+ }
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+ }
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+ }
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+
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bgmac_chip_reset(bgmac);
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err = bgmac_dma_alloc(bgmac);
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if (err) {
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bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
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--- a/drivers/net/ethernet/broadcom/bgmac.h
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+++ b/drivers/net/ethernet/broadcom/bgmac.h
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@@ -189,6 +189,7 @@
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Hauke Mehrtens
11 years ago