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@ -718,6 +718,32 @@ out: |
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return 0; |
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} |
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static void |
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ar8216_init_port(struct ar8216_priv *priv, int port) |
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{ |
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/* Enable port learning and tx */ |
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priv->write(priv, AR8216_REG_PORT_CTRL(port), |
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AR8216_PORT_CTRL_LEARN | |
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(4 << AR8216_PORT_CTRL_STATE_S)); |
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priv->write(priv, AR8216_REG_PORT_VLAN(port), 0); |
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if (port == AR8216_PORT_CPU) { |
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priv->write(priv, AR8216_REG_PORT_STATUS(port), |
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AR8216_PORT_STATUS_LINK_UP | |
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((priv->chip == AR8316) ? |
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AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) | |
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AR8216_PORT_STATUS_TXMAC | |
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AR8216_PORT_STATUS_RXMAC | |
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((priv->chip == AR8316) ? AR8216_PORT_STATUS_RXFLOW : 0) | |
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((priv->chip == AR8316) ? AR8216_PORT_STATUS_TXFLOW : 0) | |
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AR8216_PORT_STATUS_DUPLEX); |
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} else { |
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priv->write(priv, AR8216_REG_PORT_STATUS(port), |
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AR8216_PORT_STATUS_LINK_AUTO); |
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} |
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} |
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static int |
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ar8216_reset_switch(struct switch_dev *dev) |
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{ |
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@ -730,30 +756,11 @@ ar8216_reset_switch(struct switch_dev *dev) |
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for (i = 0; i < AR8X16_MAX_VLANS; i++) { |
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priv->vlan_id[i] = i; |
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} |
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for (i = 0; i < AR8216_NUM_PORTS; i++) { |
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/* Enable port learning and tx */ |
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priv->write(priv, AR8216_REG_PORT_CTRL(i), |
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AR8216_PORT_CTRL_LEARN | |
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(4 << AR8216_PORT_CTRL_STATE_S)); |
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priv->write(priv, AR8216_REG_PORT_VLAN(i), 0); |
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/* Configure all PHYs */ |
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if (i == AR8216_PORT_CPU) { |
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priv->write(priv, AR8216_REG_PORT_STATUS(i), |
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AR8216_PORT_STATUS_LINK_UP | |
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((priv->chip == AR8316) ? |
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AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) | |
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AR8216_PORT_STATUS_TXMAC | |
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AR8216_PORT_STATUS_RXMAC | |
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((priv->chip == AR8316) ? AR8216_PORT_STATUS_RXFLOW : 0) | |
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((priv->chip == AR8316) ? AR8216_PORT_STATUS_TXFLOW : 0) | |
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AR8216_PORT_STATUS_DUPLEX); |
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} else { |
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priv->write(priv, AR8216_REG_PORT_STATUS(i), |
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AR8216_PORT_STATUS_LINK_AUTO); |
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} |
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} |
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/* Configure all ports */ |
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for (i = 0; i < AR8216_NUM_PORTS; i++) |
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ar8216_init_port(priv, i); |
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/* XXX: undocumented magic from atheros, required! */ |
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priv->write(priv, 0x38, 0xc000050e); |
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