From 52109ce71f3d864775fda04284d02425b96378d8 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Wed, 13 Jun 2018 21:41:59 +0800 Subject: [PATCH] ath79: ag71xx: fix pll-data setting for ar7242/ar934x/qca955x/qca956x ar71xx/ar913x series use the old pll registers and settings. However started from ar7242, a new pll register is introduced and the pll setting is much simpler. This can be observed from dev-eth.c from the ar71xx target. Signed-off-by: Weijie Gao --- .../net/ethernet/atheros/ag71xx/ag71xx_main.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c index 656a22a4b5..feb3daf12f 100644 --- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c +++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c @@ -618,18 +618,15 @@ __ag71xx_link_adjust(struct ag71xx *ag, bool update) ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]); if (update) { - if (of_device_is_compatible(np, "qca,ar7100-eth")) { + if (of_device_is_compatible(np, "qca,ar7100-eth") || + of_device_is_compatible(np, "qca,ar9130-eth")) { ath79_set_pll(ag); ath79_mii_ctrl_set_speed(ag); - } else if (of_device_is_compatible(np, "qca,ar7242-eth")) { - ath79_set_pll(ag); - } else if (of_device_is_compatible(np, "qca,ar9130-eth")) { - ath79_set_pll(ag); - ath79_mii_ctrl_set_speed(ag); - } else if (of_device_is_compatible(np, "qca,ar9340-eth")) { - ath79_set_pll(ag); - } else if (of_device_is_compatible(np, "qca,qca9550-eth")) { - } else if (of_device_is_compatible(np, "qca,qca9560-eth")) { + } else if (of_device_is_compatible(np, "qca,ar7242-eth") || + of_device_is_compatible(np, "qca,ar9340-eth") || + of_device_is_compatible(np, "qca,qca9550-eth") || + of_device_is_compatible(np, "qca,qca9560-eth")) { + ath79_set_pllval(ag); } }