bcm6345 fixes from AndyI

SVN-Revision: 17153

target/linux/brcm63xx/files/arch/mips/bcm63xx/boards/board_bcm963xx.c

@@ -789,7 +789,9 @@ int __init board_register_devices(void)
 
 	bcm63xx_uart_register();
 	bcm63xx_wdt_register();
-	bcm63xx_spi_register();
+
+	if (!BCMCPU_IS_6345())
+		bcm63xx_spi_register();
 
 	if (board.has_pccard)
 		bcm63xx_pcmcia_register();

target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c

@@ -95,16 +95,18 @@ static const unsigned long bcm96345_regs_base[] = {
 	[RSET_UART0]		= BCM_6345_UART0_BASE,
 	[RSET_GPIO]		= BCM_6345_GPIO_BASE,
 	[RSET_SPI]		= BCM_6345_SPI_BASE,
+	[RSET_UDC0]		= BCM_6345_UDC0_BASE,
 	[RSET_OHCI0]		= BCM_6345_OHCI0_BASE,
 	[RSET_OHCI_PRIV]	= BCM_6345_OHCI_PRIV_BASE,
 	[RSET_USBH_PRIV]	= BCM_6345_USBH_PRIV_BASE,
-	[RSET_UDC0]		= BCM_6345_UDC0_BASE,
 	[RSET_MPI]		= BCM_6345_MPI_BASE,
 	[RSET_PCMCIA]		= BCM_6345_PCMCIA_BASE,
-	[RSET_SDRAM]		= BCM_6345_SDRAM_BASE,
 	[RSET_DSL]		= BCM_6345_DSL_BASE,
 	[RSET_ENET0]		= BCM_6345_ENET0_BASE,
+	[RSET_ENET1]		= BCM_6345_ENET1_BASE,
 	[RSET_ENETDMA]		= BCM_6345_ENETDMA_BASE,
+	[RSET_EHCI0]		= BCM_6345_EHCI0_BASE,
+	[RSET_SDRAM]		= BCM_6345_SDRAM_BASE,
 	[RSET_MEMC]		= BCM_6345_MEMC_BASE,
 	[RSET_DDR]		= BCM_6345_DDR_BASE,
 };

target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h

@@ -302,7 +302,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 		return BCM_6345_UART0_BASE;
 	case RSET_GPIO:
 		return BCM_6345_GPIO_BASE;
-	case RSET_SPI_BASE:
+	case RSET_SPI:
 		return BCM_6345_SPI_BASE;
 	case RSET_UDC0:
 		return BCM_6345_UDC0_BASE;
@@ -320,6 +320,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 		return BCM_6345_DSL_BASE;
 	case RSET_ENET0:
 		return BCM_6345_ENET0_BASE;
+	case RSET_ENET1:
+		return BCM_6345_ENET1_BASE;
 	case RSET_ENETDMA:
 		return BCM_6345_ENETDMA_BASE;
 	case RSET_EHCI0:
@@ -601,6 +603,16 @@ enum bcm63xx_irq {
 #define BCM_6345_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
 #define BCM_6345_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 1)
 #define BCM_6345_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 2)
+#define BCM_6345_EBI_RX_IRQ		(IRQ_INTERNAL_BASE + 13 + 5)
+#define BCM_6345_EBI_TX_IRQ		(IRQ_INTERNAL_BASE + 13 + 6)
+#define BCM_6345_RESERVED_RX_IRQ	(IRQ_INTERNAL_BASE + 13 + 9)
+#define BCM_6345_RESERVED_TX_IRQ	(IRQ_INTERNAL_BASE + 13 + 10)
+#define BCM_6345_USB_BULK_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 13)
+#define BCM_6345_USB_BULK_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 14)
+#define BCM_6345_USB_CNTL_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 15)
+#define BCM_6345_USB_CNTL_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 16)
+#define BCM_6345_USB_ISO_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 17)
+#define BCM_6345_USB_ISO_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 18)
 
 /*
  * 6348 irqs
@@ -614,12 +626,12 @@ enum bcm63xx_irq {
 #define BCM_6348_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
 #define BCM_6348_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
 #define BCM_6348_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 12)
-#define BCM_6348_USB_CNTL_RX_DMA	(IRQ_INTERNAL_BASE + 14)
-#define BCM_6348_USB_CNTL_TX_DMA	(IRQ_INTERNAL_BASE + 15)
-#define BCM_6348_USB_BULK_RX_DMA	(IRQ_INTERNAL_BASE + 16)
-#define BCM_6348_USB_BULK_TX_DMA	(IRQ_INTERNAL_BASE + 17)
-#define BCM_6348_USB_ISO_RX_DMA		(IRQ_INTERNAL_BASE + 18)
-#define BCM_6348_USB_ISO_TX_DMA		(IRQ_INTERNAL_BASE + 19)
+#define BCM_6348_USB_CNTL_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 14)
+#define BCM_6348_USB_CNTL_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 15)
+#define BCM_6348_USB_BULK_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 16)
+#define BCM_6348_USB_BULK_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 17)
+#define BCM_6348_USB_ISO_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 18)
+#define BCM_6348_USB_ISO_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 19)
 #define BCM_6348_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 20)
 #define BCM_6348_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 21)
 #define BCM_6348_ENET1_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 22)

target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h

@@ -734,6 +734,8 @@
 #define SDRAM_CFG_BANK_SHIFT		13
 #define SDRAM_CFG_BANK_MASK		(1 << SDRAM_CFG_BANK_SHIFT)
 
+#define SDRAM_MEM_REG			0xc
+
 #define SDRAM_PRIO_REG			0x2C
 #define SDRAM_PRIO_MIPS_SHIFT		29
 #define SDRAM_PRIO_MIPS_MASK		(1 << SDRAM_PRIO_MIPS_SHIFT)