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@ -83,6 +83,8 @@ static int mt7620_mdio_mode(struct device_node *eth_node) |
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static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode) |
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{ |
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u32 i; |
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u32 val; |
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u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1; |
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rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1); |
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@ -151,6 +153,14 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode) |
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/* global page 1 */ |
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_mt7620_mii_write(gsw, 1, 31, 0x1000); |
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_mt7620_mii_write(gsw, 1, 17, 0xe7f8); |
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/* turn on all PHYs */ |
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for (i = 0; i <= 4; i++) { |
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val = _mt7620_mii_read(gsw, i, 0); |
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val &= ~BIT(11); |
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_mt7620_mii_write(gsw, i, 0, val); |
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} |
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} |
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/* global page 0 */ |
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@ -187,7 +197,6 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode) |
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_mt7620_mii_write(gsw, 4, 30, 0xa000); |
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_mt7620_mii_write(gsw, 4, 4, 0x05e1); |
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_mt7620_mii_write(gsw, 4, 16, 0x1313); |
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_mt7620_mii_write(gsw, 4, 0, 0x3100); |
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pr_info("gsw: setting port4 to ephy mode\n"); |
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} else if (!mdio_mode) { |
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u32 val = rt_sysc_r32(SYSC_REG_CFG1); |
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