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@ -33,65 +33,68 @@ |
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#define DMA_RX_EV2 AR_BIT(5) |
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#define DMA_RX_ERR_COL AR_BIT(6) |
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#define DMA_RX_LONG AR_BIT(7) |
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#define DMA_RX_LS AR_BIT(8) /* last descriptor */ |
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#define DMA_RX_FS AR_BIT(9) /* first descriptor */ |
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#define DMA_RX_MF AR_BIT(10) /* multicast frame */ |
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#define DMA_RX_ERR_RUNT AR_BIT(11) /* runt frame */ |
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#define DMA_RX_ERR_LENGTH AR_BIT(12) /* length error */ |
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#define DMA_RX_ERR_DESC AR_BIT(14) /* descriptor error */ |
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#define DMA_RX_ERROR AR_BIT(15) /* error summary */ |
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#define DMA_RX_LS AR_BIT(8) /* last descriptor */ |
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#define DMA_RX_FS AR_BIT(9) /* first descriptor */ |
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#define DMA_RX_MF AR_BIT(10) /* multicast frame */ |
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#define DMA_RX_ERR_RUNT AR_BIT(11) /* runt frame */ |
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#define DMA_RX_ERR_LENGTH AR_BIT(12) /* length error */ |
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#define DMA_RX_ERR_DESC AR_BIT(14) /* descriptor error */ |
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#define DMA_RX_ERROR AR_BIT(15) /* error summary */ |
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#define DMA_RX_LEN_MASK 0x3fff0000 |
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#define DMA_RX_LEN_SHIFT 16 |
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#define DMA_RX_FILT AR_BIT(30) |
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#define DMA_RX_OWN AR_BIT(31) /* desc owned by DMA controller */ |
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#define DMA_RX_OWN AR_BIT(31) /* desc owned by DMA controller */ |
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#define DMA_RX1_BSIZE_MASK 0x000007ff |
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#define DMA_RX1_BSIZE_SHIFT 0 |
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#define DMA_RX1_CHAINED AR_BIT(24) |
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#define DMA_RX1_RER AR_BIT(25) |
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#define DMA_TX_ERR_UNDER AR_BIT(1) /* underflow error */ |
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#define DMA_TX_ERR_DEFER AR_BIT(2) /* excessive deferral */ |
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#define DMA_TX_ERR_UNDER AR_BIT(1) /* underflow error */ |
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#define DMA_TX_ERR_DEFER AR_BIT(2) /* excessive deferral */ |
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#define DMA_TX_COL_MASK 0x78 |
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#define DMA_TX_COL_SHIFT 3 |
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#define DMA_TX_ERR_HB AR_BIT(7) /* hearbeat failure */ |
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#define DMA_TX_ERR_COL AR_BIT(8) /* excessive collisions */ |
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#define DMA_TX_ERR_LATE AR_BIT(9) /* late collision */ |
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#define DMA_TX_ERR_LINK AR_BIT(10) /* no carrier */ |
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#define DMA_TX_ERR_LOSS AR_BIT(11) /* loss of carrier */ |
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#define DMA_TX_ERR_JABBER AR_BIT(14) /* transmit jabber timeout */ |
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#define DMA_TX_ERROR AR_BIT(15) /* frame aborted */ |
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#define DMA_TX_OWN AR_BIT(31) /* descr owned by DMA controller */ |
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#define DMA_TX_ERR_HB AR_BIT(7) /* hearbeat failure */ |
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#define DMA_TX_ERR_COL AR_BIT(8) /* excessive collisions */ |
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#define DMA_TX_ERR_LATE AR_BIT(9) /* late collision */ |
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#define DMA_TX_ERR_LINK AR_BIT(10) /* no carrier */ |
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#define DMA_TX_ERR_LOSS AR_BIT(11) /* loss of carrier */ |
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#define DMA_TX_ERR_JABBER AR_BIT(14) /* transmit jabber timeout */ |
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#define DMA_TX_ERROR AR_BIT(15) /* frame aborted */ |
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#define DMA_TX_OWN AR_BIT(31) /* descr owned by DMA controller */ |
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#define DMA_TX1_BSIZE_MASK 0x000007ff |
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#define DMA_TX1_BSIZE_SHIFT 0 |
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#define DMA_TX1_CHAINED AR_BIT(24) /* chained descriptors */ |
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#define DMA_TX1_TER AR_BIT(25) /* transmit end of ring */ |
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#define DMA_TX1_FS AR_BIT(29) /* first segment */ |
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#define DMA_TX1_LS AR_BIT(30) /* last segment */ |
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#define DMA_TX1_IC AR_BIT(31) /* interrupt on completion */ |
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#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ |
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#define MAC_CONTROL_RE AR_BIT(2) /* receive enable */ |
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#define MAC_CONTROL_TE AR_BIT(3) /* transmit enable */ |
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#define MAC_CONTROL_DC AR_BIT(5) /* Deferral check*/ |
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#define MAC_CONTROL_ASTP AR_BIT(8) /* Auto pad strip */ |
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#define MAC_CONTROL_DRTY AR_BIT(10) /* Disable retry */ |
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#define MAC_CONTROL_DBF AR_BIT(11) /* Disable bcast frames */ |
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#define MAC_CONTROL_LCC AR_BIT(12) /* late collision ctrl */ |
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#define MAC_CONTROL_HP AR_BIT(13) /* Hash Perfect filtering */ |
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#define MAC_CONTROL_HASH AR_BIT(14) /* Unicast hash filtering */ |
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#define MAC_CONTROL_HO AR_BIT(15) /* Hash only filtering */ |
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#define MAC_CONTROL_PB AR_BIT(16) /* Pass Bad frames */ |
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#define MAC_CONTROL_IF AR_BIT(17) /* Inverse filtering */ |
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#define MAC_CONTROL_PR AR_BIT(18) /* promiscuous mode (valid frames only) */ |
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#define MAC_CONTROL_PM AR_BIT(19) /* pass multicast */ |
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#define MAC_CONTROL_F AR_BIT(20) /* full-duplex */ |
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#define MAC_CONTROL_DRO AR_BIT(23) /* Disable Receive Own */ |
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#define MAC_CONTROL_HBD AR_BIT(28) /* heart-beat disabled (MUST BE SET) */ |
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#define MAC_CONTROL_BLE AR_BIT(30) /* big endian mode */ |
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#define MAC_CONTROL_RA AR_BIT(31) /* receive all (valid and invalid frames) */ |
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#define DMA_TX1_CHAINED AR_BIT(24) /* chained descriptors */ |
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#define DMA_TX1_TER AR_BIT(25) /* transmit end of ring */ |
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#define DMA_TX1_FS AR_BIT(29) /* first segment */ |
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#define DMA_TX1_LS AR_BIT(30) /* last segment */ |
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#define DMA_TX1_IC AR_BIT(31) /* interrupt on completion */ |
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#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ |
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#define MAC_CONTROL_RE AR_BIT(2) /* receive enable */ |
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#define MAC_CONTROL_TE AR_BIT(3) /* transmit enable */ |
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#define MAC_CONTROL_DC AR_BIT(5) /* Deferral check */ |
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#define MAC_CONTROL_ASTP AR_BIT(8) /* Auto pad strip */ |
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#define MAC_CONTROL_DRTY AR_BIT(10) /* Disable retry */ |
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#define MAC_CONTROL_DBF AR_BIT(11) /* Disable bcast frames */ |
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#define MAC_CONTROL_LCC AR_BIT(12) /* late collision ctrl */ |
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#define MAC_CONTROL_HP AR_BIT(13) /* Hash Perfect filtering */ |
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#define MAC_CONTROL_HASH AR_BIT(14) /* Unicast hash filtering */ |
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#define MAC_CONTROL_HO AR_BIT(15) /* Hash only filtering */ |
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#define MAC_CONTROL_PB AR_BIT(16) /* Pass Bad frames */ |
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#define MAC_CONTROL_IF AR_BIT(17) /* Inverse filtering */ |
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#define MAC_CONTROL_PR AR_BIT(18) /* promiscuous mode (valid frames |
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only) */ |
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#define MAC_CONTROL_PM AR_BIT(19) /* pass multicast */ |
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#define MAC_CONTROL_F AR_BIT(20) /* full-duplex */ |
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#define MAC_CONTROL_DRO AR_BIT(23) /* Disable Receive Own */ |
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#define MAC_CONTROL_HBD AR_BIT(28) /* heart-beat disabled (MUST BE |
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SET) */ |
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#define MAC_CONTROL_BLE AR_BIT(30) /* big endian mode */ |
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#define MAC_CONTROL_RA AR_BIT(31) /* receive all (valid and invalid |
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frames) */ |
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#define MII_ADDR_BUSY AR_BIT(0) |
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#define MII_ADDR_WRITE AR_BIT(1) |
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@ -101,40 +104,39 @@ |
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#define FLOW_CONTROL_FCE AR_BIT(1) |
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#define DMA_BUS_MODE_SWR AR_BIT(0) /* software reset */ |
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#define DMA_BUS_MODE_BLE AR_BIT(7) /* big endian mode */ |
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#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ |
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#define DMA_BUS_MODE_DBO AR_BIT(20) /* big-endian descriptors */ |
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#define DMA_STATUS_TI AR_BIT(0) /* transmit interrupt */ |
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#define DMA_STATUS_TPS AR_BIT(1) /* transmit process stopped */ |
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#define DMA_STATUS_TU AR_BIT(2) /* transmit buffer unavailable */ |
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#define DMA_STATUS_TJT AR_BIT(3) /* transmit buffer timeout */ |
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#define DMA_STATUS_UNF AR_BIT(5) /* transmit underflow */ |
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#define DMA_STATUS_RI AR_BIT(6) /* receive interrupt */ |
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#define DMA_STATUS_RU AR_BIT(7) /* receive buffer unavailable */ |
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#define DMA_STATUS_RPS AR_BIT(8) /* receive process stopped */ |
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#define DMA_STATUS_ETI AR_BIT(10) /* early transmit interrupt */ |
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#define DMA_STATUS_FBE AR_BIT(13) /* fatal bus interrupt */ |
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#define DMA_STATUS_ERI AR_BIT(14) /* early receive interrupt */ |
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#define DMA_STATUS_AIS AR_BIT(15) /* abnormal interrupt summary */ |
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#define DMA_STATUS_NIS AR_BIT(16) /* normal interrupt summary */ |
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#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ |
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#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ |
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#define DMA_STATUS_EB_SHIFT 23 /* error bits */ |
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#define DMA_CONTROL_SR AR_BIT(1) /* start receive */ |
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#define DMA_CONTROL_ST AR_BIT(13) /* start transmit */ |
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#define DMA_CONTROL_SF AR_BIT(21) /* store and forward */ |
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#define DMA_BUS_MODE_SWR AR_BIT(0) /* software reset */ |
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#define DMA_BUS_MODE_BLE AR_BIT(7) /* big endian mode */ |
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#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ |
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#define DMA_BUS_MODE_DBO AR_BIT(20) /* big-endian descriptors */ |
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#define DMA_STATUS_TI AR_BIT(0) /* transmit interrupt */ |
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#define DMA_STATUS_TPS AR_BIT(1) /* transmit process stopped */ |
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#define DMA_STATUS_TU AR_BIT(2) /* transmit buffer unavailable */ |
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#define DMA_STATUS_TJT AR_BIT(3) /* transmit buffer timeout */ |
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#define DMA_STATUS_UNF AR_BIT(5) /* transmit underflow */ |
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#define DMA_STATUS_RI AR_BIT(6) /* receive interrupt */ |
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#define DMA_STATUS_RU AR_BIT(7) /* receive buffer unavailable */ |
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#define DMA_STATUS_RPS AR_BIT(8) /* receive process stopped */ |
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#define DMA_STATUS_ETI AR_BIT(10) /* early transmit interrupt */ |
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#define DMA_STATUS_FBE AR_BIT(13) /* fatal bus interrupt */ |
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#define DMA_STATUS_ERI AR_BIT(14) /* early receive interrupt */ |
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#define DMA_STATUS_AIS AR_BIT(15) /* abnormal interrupt summary */ |
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#define DMA_STATUS_NIS AR_BIT(16) /* normal interrupt summary */ |
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#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ |
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#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ |
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#define DMA_STATUS_EB_SHIFT 23 /* error bits */ |
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#define DMA_CONTROL_SR AR_BIT(1) /* start receive */ |
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#define DMA_CONTROL_ST AR_BIT(13) /* start transmit */ |
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#define DMA_CONTROL_SF AR_BIT(21) /* store and forward */ |
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typedef struct { |
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volatile unsigned int status; // OWN, Device control and status.
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volatile unsigned int devcs; // pkt Control bits + Length
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volatile unsigned int addr; // Current Address.
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volatile unsigned int descr; // Next descriptor in chain.
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volatile unsigned int status; // OWN, Device control and status.
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volatile unsigned int devcs; // pkt Control bits + Length
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volatile unsigned int addr; // Current Address.
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volatile unsigned int descr; // Next descriptor in chain.
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} ar2313_descr_t; |
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#endif // __ARUBA_DMA_H__
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#endif // __ARUBA_DMA_H__
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Felix Fietkau
18 years ago