John Crispin
16 years ago
parent
7866f69cbe
commit
3e2c38b0fb
@ -1,15 +1,29 @@ |
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/*
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
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* |
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*/ |
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#ifndef _IFXMIPS_CGU_H__ |
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#define _IFXMIPS_CGU_H__ |
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u32 cgu_get_mips_clock(int cpu); |
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u32 cgu_get_cpu_clock(void); |
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u32 cgu_get_io_region_clock(void); |
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u32 cgu_get_fpi_bus_clock(int fpi); |
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u32 cgu_get_pp32_clock(void); |
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u32 cgu_get_ethernet_clock(int mii); |
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u32 cgu_get_usb_clock(void); |
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u32 cgu_get_clockout(int clkout); |
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unsigned int cgu_get_mips_clock(int cpu); |
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unsigned int cgu_get_io_region_clock(void); |
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unsigned int cgu_get_fpi_bus_clock(int fpi); |
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void cgu_setup_pci_clk(int internal_clock); |
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u32 ifxmips_get_ddr_hz(void); |
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u32 ifxmips_get_cpu_hz(void); |
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u32 ifxmips_get_fpi_hz(void); |
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unsigned int ifxmips_get_ddr_hz(void); |
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unsigned int ifxmips_get_fpi_hz(void); |
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unsigned int ifxmips_get_cpu_hz(void); |
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#endif |
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@ -1,42 +0,0 @@ |
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/*
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
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* |
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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* |
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*/ |
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#ifndef _IFXMIPS_IOCTL_H__ |
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#define _IFXMIPS_IOCTL_H__ |
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/*------------ LED */ |
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struct ifxmips_port_ioctl_parm |
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{ |
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int port; |
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int pin; |
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int value; |
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}; |
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#define IFXMIPS_PORT_IOC_MAGIC 0xbf |
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#define IFXMIPS_PORT_IOCOD _IOW(IFXMIPS_PORT_IOC_MAGIC,0,struct ifxmips_port_ioctl_parm) |
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#define IFXMIPS_PORT_IOCPUDSEL _IOW(IFXMIPS_PORT_IOC_MAGIC,1,struct ifxmips_port_ioctl_parm) |
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#define IFXMIPS_PORT_IOCPUDEN _IOW(IFXMIPS_PORT_IOC_MAGIC,2,struct ifxmips_port_ioctl_parm) |
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#define IFXMIPS_PORT_IOCSTOFF _IOW(IFXMIPS_PORT_IOC_MAGIC,3,struct ifxmips_port_ioctl_parm) |
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#define IFXMIPS_PORT_IOCDIR _IOW(IFXMIPS_PORT_IOC_MAGIC,4,struct ifxmips_port_ioctl_parm) |
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#define IFXMIPS_PORT_IOCOUTPUT _IOW(IFXMIPS_PORT_IOC_MAGIC,5,struct ifxmips_port_ioctl_parm) |
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#define IFXMIPS_PORT_IOCINPUT _IOWR(IFXMIPS_PORT_IOC_MAGIC,6,struct ifxmips_port_ioctl_parm) |
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#define IFXMIPS_PORT_IOCALTSEL0 _IOW(IFXMIPS_PORT_IOC_MAGIC,7,struct ifxmips_port_ioctl_parm) |
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#define IFXMIPS_PORT_IOCALTSEL1 _IOW(IFXMIPS_PORT_IOC_MAGIC,8,struct ifxmips_port_ioctl_parm) |
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#endif |
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@ -1,34 +0,0 @@ |
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#ifndef IFXMIPS_MII0_H |
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#define IFXMIPS_MII0_H |
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/*
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
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* |
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*/ |
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#include <linux/netdevice.h> |
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struct ifxmips_mii_priv { |
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struct net_device_stats stats; |
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struct dma_device_info *dma_device; |
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struct sk_buff *skb; |
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}; |
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struct ifxmips_mac { |
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unsigned char mac[6]; |
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}; |
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#endif |
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Load Diff
@ -1,194 +0,0 @@ |
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/* incaAscSio.h - (IFXMIPS) ASC UART tty driver header */ |
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#ifndef __IFXMIPS_ASC_H |
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#define __IFXMIPS_ASC_H |
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/******************************************************************************
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** |
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** FILE NAME : serial.c |
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** PROJECT : IFXMips |
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** MODULES : ASC/UART |
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** |
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** DATE : 27 MAR 2006 |
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** AUTHOR : Liu Peng |
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** DESCRIPTION : Asynchronous Serial Channel (ASC/UART) Driver Header File |
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** COPYRIGHT : Copyright (c) 2006 |
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** Infineon Technologies AG |
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** Am Campeon 1-12, 85579 Neubiberg, Germany |
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** |
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** This program is free software; you can redistribute it and/or modify |
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** it under the terms of the GNU General Public License as published by |
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** the Free Software Foundation; either version 2 of the License, or |
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** (at your option) any later version. |
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** |
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** HISTORY |
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** $Date $Author $Comment |
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** 27 MAR 2006 Liu Peng Initiate Version (rev 1.7) |
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** 23 OCT 2006 Xu Liang Add GPL header. |
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*******************************************************************************/ |
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/* channel operating modes */ |
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/*#define ASCOPT_CSIZE 0x00000003
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#define ASCOPT_CS7 0x00000001 |
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#define ASCOPT_CS8 0x00000002 |
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#define ASCOPT_PARENB 0x00000004 |
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#define ASCOPT_STOPB 0x00000008 |
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#define ASCOPT_PARODD 0x00000010 |
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#define ASCOPT_CREAD 0x00000020 |
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*/ |
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#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) |
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/* ASC input select (0 or 1) */ |
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#define CONSOLE_TTY 0 |
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#define IFXMIPSASC_TXFIFO_FL 1 |
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#define IFXMIPSASC_RXFIFO_FL 1 |
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#define IFXMIPSASC_TXFIFO_FULL 16 |
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/* interrupt lines masks for the ASC device interrupts*/ |
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/* change these macroses if it's necessary */ |
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#define IFXMIPSASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */ |
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#define IFXMIPSASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */ |
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#define IFXMIPSASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */ |
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#define IFXMIPSASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */ |
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#define IFXMIPSASC_IRQ_LINE_EIR 0x00000008 /* Error Int */ |
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#define IFXMIPSASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */ |
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#define IFXMIPSASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */ |
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#define IFXMIPSASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */ |
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/* interrupt controller access macros */ |
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#define ASC_INTERRUPTS_ENABLE(X) \ |
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*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) |= X; |
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#define ASC_INTERRUPTS_DISABLE(X) \ |
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*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) &= ~X; |
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#define ASC_INTERRUPTS_CLEAR(X) \ |
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*((volatile unsigned int*) IFXMIPS_ICU_IM0_ISR) = X; |
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/* CLC register's bits and bitfields */ |
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#define ASCCLC_DISR 0x00000001 |
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#define ASCCLC_DISS 0x00000002 |
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#define ASCCLC_RMCMASK 0x0000FF00 |
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#define ASCCLC_RMCOFFSET 8 |
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/* CON register's bits and bitfields */ |
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#define ASCCON_MODEMASK 0x0000000f |
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#define ASCCON_M_8ASYNC 0x0 |
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#define ASCCON_M_8IRDA 0x1 |
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#define ASCCON_M_7ASYNC 0x2 |
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#define ASCCON_M_7IRDA 0x3 |
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#define ASCCON_WLSMASK 0x0000000c |
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#define ASCCON_WLSOFFSET 2 |
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#define ASCCON_WLS_8BIT 0x0 |
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#define ASCCON_WLS_7BIT 0x1 |
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#define ASCCON_PEN 0x00000010 |
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#define ASCCON_ODD 0x00000020 |
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#define ASCCON_SP 0x00000040 |
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#define ASCCON_STP 0x00000080 |
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#define ASCCON_BRS 0x00000100 |
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#define ASCCON_FDE 0x00000200 |
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#define ASCCON_ERRCLK 0x00000400 |
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#define ASCCON_EMMASK 0x00001800 |
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#define ASCCON_EMOFFSET 11 |
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#define ASCCON_EM_ECHO_OFF 0x0 |
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#define ASCCON_EM_ECHO_AB 0x1 |
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#define ASCCON_EM_ECHO_ON 0x2 |
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#define ASCCON_LB 0x00002000 |
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#define ASCCON_ACO 0x00004000 |
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#define ASCCON_R 0x00008000 |
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#define ASCCON_PAL 0x00010000 |
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#define ASCCON_FEN 0x00020000 |
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#define ASCCON_RUEN 0x00040000 |
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#define ASCCON_ROEN 0x00080000 |
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#define ASCCON_TOEN 0x00100000 |
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#define ASCCON_BEN 0x00200000 |
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#define ASCCON_TXINV 0x01000000 |
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#define ASCCON_RXINV 0x02000000 |
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#define ASCCON_TXMSB 0x04000000 |
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#define ASCCON_RXMSB 0x08000000 |
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/* STATE register's bits and bitfields */ |
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#define ASCSTATE_REN 0x00000001 |
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#define ASCSTATE_PE 0x00010000 |
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#define ASCSTATE_FE 0x00020000 |
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#define ASCSTATE_RUE 0x00040000 |
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#define ASCSTATE_ROE 0x00080000 |
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#define ASCSTATE_TOE 0x00100000 |
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#define ASCSTATE_BE 0x00200000 |
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#define ASCSTATE_TXBVMASK 0x07000000 |
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#define ASCSTATE_TXBVOFFSET 24 |
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#define ASCSTATE_TXEOM 0x08000000 |
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#define ASCSTATE_RXBVMASK 0x70000000 |
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#define ASCSTATE_RXBVOFFSET 28 |
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#define ASCSTATE_RXEOM 0x80000000 |
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#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) |
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/* WHBSTATE register's bits and bitfields */ |
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#define ASCWHBSTATE_CLRREN 0x00000001 |
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#define ASCWHBSTATE_SETREN 0x00000002 |
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#define ASCWHBSTATE_CLRPE 0x00000004 |
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#define ASCWHBSTATE_CLRFE 0x00000008 |
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#define ASCWHBSTATE_CLRRUE 0x00000010 |
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#define ASCWHBSTATE_CLRROE 0x00000020 |
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#define ASCWHBSTATE_CLRTOE 0x00000040 |
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#define ASCWHBSTATE_CLRBE 0x00000080 |
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#define ASCWHBSTATE_SETPE 0x00000100 |
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#define ASCWHBSTATE_SETFE 0x00000200 |
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#define ASCWHBSTATE_SETRUE 0x00000400 |
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#define ASCWHBSTATE_SETROE 0x00000800 |
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#define ASCWHBSTATE_SETTOE 0x00001000 |
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#define ASCWHBSTATE_SETBE 0x00002000 |
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/* ABCON register's bits and bitfields */ |
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#define ASCABCON_ABEN 0x0001 |
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#define ASCABCON_AUREN 0x0002 |
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#define ASCABCON_ABSTEN 0x0004 |
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#define ASCABCON_ABDETEN 0x0008 |
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#define ASCABCON_FCDETEN 0x0010 |
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/* FDV register mask, offset and bitfields*/ |
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#define ASCFDV_VALUE_MASK 0x000001FF |
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/* WHBABCON register's bits and bitfields */ |
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#define ASCWHBABCON_CLRABEN 0x0001 |
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#define ASCWHBABCON_SETABEN 0x0002 |
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/* ABSTAT register's bits and bitfields */ |
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#define ASCABSTAT_FCSDET 0x0001 |
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#define ASCABSTAT_FCCDET 0x0002 |
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#define ASCABSTAT_SCSDET 0x0004 |
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#define ASCABSTAT_SCCDET 0x0008 |
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#define ASCABSTAT_DETWAIT 0x0010 |
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/* WHBABSTAT register's bits and bitfields */ |
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#define ASCWHBABSTAT_CLRFCSDET 0x0001 |
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#define ASCWHBABSTAT_SETFCSDET 0x0002 |
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#define ASCWHBABSTAT_CLRFCCDET 0x0004 |
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#define ASCWHBABSTAT_SETFCCDET 0x0008 |
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#define ASCWHBABSTAT_CLRSCSDET 0x0010 |
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#define ASCWHBABSTAT_SETSCSDET 0x0020 |
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#define ASCWHBABSTAT_CLRSCCDET 0x0040 |
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#define ASCWHBABSTAT_SETSCCDET 0x0080 |
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#define ASCWHBABSTAT_CLRDETWAIT 0x0100 |
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#define ASCWHBABSTAT_SETDETWAIT 0x0200 |
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/* TXFCON register's bits and bitfields */ |
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#define ASCTXFCON_TXFIFO1 0x00000400 |
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#define ASCTXFCON_TXFEN 0x0001 |
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#define ASCTXFCON_TXFFLU 0x0002 |
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#define ASCTXFCON_TXFITLMASK 0x3F00 |
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#define ASCTXFCON_TXFITLOFF 8 |
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/* RXFCON register's bits and bitfields */ |
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#define ASCRXFCON_RXFIFO1 0x00000400 |
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#define ASCRXFCON_RXFEN 0x0001 |
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#define ASCRXFCON_RXFFLU 0x0002 |
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#define ASCRXFCON_RXFITLMASK 0x3F00 |
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#define ASCRXFCON_RXFITLOFF 8 |
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/* FSTAT register's bits and bitfields */ |
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#define ASCFSTAT_RXFFLMASK 0x003F |
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#define ASCFSTAT_TXFFLMASK 0x3F00 |
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#define ASCFSTAT_TXFFLOFF 8 |
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#endif /* __IFXMIPS_ASC_H */ |
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