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@ -1,7 +1,7 @@ |
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/*
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* NAND flash driver for the MikroTik RouterBOARD 91x series |
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* |
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
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* Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 as published |
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@ -17,35 +17,38 @@ |
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#include <linux/platform_device.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/gpio.h> |
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#include <linux/platform_data/rb91x_nand.h> |
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#include <asm/mach-ath79/ar71xx_regs.h> |
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#include <asm/mach-ath79/ath79.h> |
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#define DRV_NAME "rb91x-nand" |
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#define DRV_DESC "NAND flash driver for the RouterBOARD 91x series" |
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#define RB91X_NAND_NRE_ENABLE BIT(3) |
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#define RB91X_NAND_RDY BIT(4) |
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#define RB91X_LATCH_ENABLE BIT(11) |
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#define RB91X_NAND_NRWE BIT(12) |
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#define RB91X_NAND_NCE BIT(13) |
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#define RB91X_NAND_CLE BIT(14) |
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#define RB91X_NAND_ALE BIT(15) |
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#define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\ |
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BIT(13) | BIT(14) | BIT(15)) |
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#define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY) |
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#define RB91X_NAND_OUTPUT_BITS \ |
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(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE) |
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#define RB91X_NAND_OUTPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE) |
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#define RB91X_NAND_LOW_DATA_MASK 0x1f |
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#define RB91X_NAND_HIGH_DATA_MASK 0xe0 |
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#define RB91X_NAND_HIGH_DATA_SHIFT 8 |
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struct rb91x_nand_info { |
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struct nand_chip chip; |
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struct mtd_info mtd; |
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struct nand_chip chip; |
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struct mtd_info mtd; |
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struct device *dev; |
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int gpio_nce; |
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int gpio_ale; |
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int gpio_cle; |
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int gpio_rdy; |
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int gpio_read; |
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int gpio_nrw; |
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int gpio_nle; |
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}; |
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static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd) |
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@ -81,53 +84,9 @@ static struct mtd_partition rb91x_nand_partitions[] = { |
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}, |
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}; |
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static void rb91x_change_gpo(u32 clear, u32 set) |
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{ |
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void __iomem *base = ath79_gpio_base; |
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static unsigned on = 0xE002800; |
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static unsigned off = 0x0000C008; |
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static unsigned oe = 0; |
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static DEFINE_SPINLOCK(lock); |
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unsigned long flags; |
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spin_lock_irqsave(&lock, flags); |
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on = (on | set) & ~clear; |
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off = (off | clear) & ~set; |
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if (!oe) |
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oe = __raw_readl(base + AR71XX_GPIO_REG_OE); |
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if (on & RB91X_LATCH_ENABLE) { |
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u32 t; |
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t = oe & __raw_readl(base + AR71XX_GPIO_REG_OE); |
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t &= ~(on | off); |
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__raw_writel(t, base + AR71XX_GPIO_REG_OE); |
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__raw_writel(off, base + AR71XX_GPIO_REG_CLEAR); |
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__raw_writel(on, base + AR71XX_GPIO_REG_SET); |
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} else if (clear & RB91X_LATCH_ENABLE) { |
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oe = __raw_readl(base + AR71XX_GPIO_REG_OE); |
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__raw_writel(RB91X_LATCH_ENABLE, |
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base + AR71XX_GPIO_REG_CLEAR); |
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/* flush write */ |
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__raw_readl(base + AR71XX_GPIO_REG_CLEAR); |
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} |
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spin_unlock_irqrestore(&lock, flags); |
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} |
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static inline void rb91x_latch_enable(void) |
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{ |
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rb91x_change_gpo(RB91X_LATCH_ENABLE, 0); |
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} |
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static inline void rb91x_latch_disable(void) |
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{ |
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rb91x_change_gpo(0, RB91X_LATCH_ENABLE); |
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} |
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static void rb91x_nand_write(const u8 *buf, unsigned len) |
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static void rb91x_nand_write(struct rb91x_nand_info *rbni, |
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const u8 *buf, |
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unsigned len) |
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{ |
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void __iomem *base = ath79_gpio_base; |
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u32 oe_reg; |
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@ -135,7 +94,8 @@ static void rb91x_nand_write(const u8 *buf, unsigned len) |
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u32 out; |
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unsigned i; |
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rb91x_latch_enable(); |
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/* enable the latch */ |
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gpio_set_value_cansleep(rbni->gpio_nle, 0); |
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oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE); |
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out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT); |
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@ -162,30 +122,32 @@ static void rb91x_nand_write(const u8 *buf, unsigned len) |
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} |
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/* restore registers */ |
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__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE); |
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__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT); |
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__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE); |
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/* flush write */ |
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__raw_readl(base + AR71XX_GPIO_REG_OUT); |
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rb91x_latch_disable(); |
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/* disable the latch */ |
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gpio_set_value_cansleep(rbni->gpio_nle, 1); |
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} |
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static void rb91x_nand_read(u8 *read_buf, unsigned len) |
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static void rb91x_nand_read(struct rb91x_nand_info *rbni, |
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u8 *read_buf, |
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unsigned len) |
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{ |
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void __iomem *base = ath79_gpio_base; |
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u32 oe_reg; |
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u32 out_reg; |
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unsigned i; |
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/* save registers */ |
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oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE); |
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/* select nRE mode */ |
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rb91x_change_gpo(0, RB91X_NAND_NRE_ENABLE); |
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/* enable read mode */ |
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gpio_set_value_cansleep(rbni->gpio_read, 1); |
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/* enable latch */ |
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rb91x_latch_enable(); |
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gpio_set_value_cansleep(rbni->gpio_nle, 0); |
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/* save registers */ |
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oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE); |
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out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT); |
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/* set data lines to input mode */ |
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@ -215,109 +177,169 @@ static void rb91x_nand_read(u8 *read_buf, unsigned len) |
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} |
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/* restore registers */ |
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__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE); |
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__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT); |
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__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE); |
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/* flush write */ |
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__raw_readl(base + AR71XX_GPIO_REG_OUT); |
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/* disable latch */ |
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rb91x_latch_disable(); |
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gpio_set_value_cansleep(rbni->gpio_nle, 1); |
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/* deselect nRE mode */ |
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rb91x_change_gpo(RB91X_NAND_NRE_ENABLE, 0); |
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/* disable read mode */ |
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gpio_set_value_cansleep(rbni->gpio_read, 0); |
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} |
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static int rb91x_nand_dev_ready(struct mtd_info *mtd) |
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{ |
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void __iomem *base = ath79_gpio_base; |
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struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); |
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return !!(__raw_readl(base + AR71XX_GPIO_REG_IN) & RB91X_NAND_RDY); |
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return gpio_get_value_cansleep(rbni->gpio_rdy); |
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} |
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static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, |
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unsigned int ctrl) |
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{ |
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if (ctrl & NAND_CTRL_CHANGE) { |
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u32 on = 0; |
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u32 off; |
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if (!(ctrl & NAND_NCE)) |
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on |= RB91X_NAND_NCE; |
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if (ctrl & NAND_CLE) |
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on |= RB91X_NAND_CLE; |
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if (ctrl & NAND_ALE) |
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on |= RB91X_NAND_ALE; |
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struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); |
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off = on ^ (RB91X_NAND_ALE | RB91X_NAND_NCE | RB91X_NAND_CLE); |
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rb91x_change_gpo(off, on); |
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if (ctrl & NAND_CTRL_CHANGE) { |
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gpio_set_value_cansleep(rbni->gpio_cle, |
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(ctrl & NAND_CLE) ? 1 : 0); |
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gpio_set_value_cansleep(rbni->gpio_ale, |
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(ctrl & NAND_ALE) ? 1 : 0); |
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gpio_set_value_cansleep(rbni->gpio_nce, |
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(ctrl & NAND_NCE) ? 0 : 1); |
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} |
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if (cmd != NAND_CMD_NONE) { |
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u8 t = cmd; |
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rb91x_nand_write(&t, 1); |
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rb91x_nand_write(rbni, &t, 1); |
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} |
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} |
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static u8 rb91x_nand_read_byte(struct mtd_info *mtd) |
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{ |
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struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); |
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u8 data = 0xff; |
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rb91x_nand_read(&data, 1); |
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rb91x_nand_read(rbni, &data, 1); |
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return data; |
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} |
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static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) |
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{ |
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rb91x_nand_read(buf, len); |
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struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); |
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rb91x_nand_read(rbni, buf, len); |
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} |
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static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) |
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{ |
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rb91x_nand_write(buf, len); |
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struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); |
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rb91x_nand_write(rbni, buf, len); |
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} |
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static int rb91x_nand_gpio_init(struct rb91x_nand_info *info) |
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{ |
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int ret; |
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/*
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* Ensure that the LATCH is disabled before initializing |
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* control lines. |
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*/ |
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ret = devm_gpio_request_one(info->dev, info->gpio_nle, |
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GPIOF_OUT_INIT_HIGH, "LATCH enable"); |
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if (ret) |
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return ret; |
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ret = devm_gpio_request_one(info->dev, info->gpio_nce, |
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GPIOF_OUT_INIT_HIGH, "NAND nCE"); |
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if (ret) |
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return ret; |
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ret = devm_gpio_request_one(info->dev, info->gpio_nrw, |
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GPIOF_OUT_INIT_HIGH, "NAND nRW"); |
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if (ret) |
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return ret; |
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ret = devm_gpio_request_one(info->dev, info->gpio_cle, |
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GPIOF_OUT_INIT_LOW, "NAND CLE"); |
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if (ret) |
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return ret; |
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ret = devm_gpio_request_one(info->dev, info->gpio_ale, |
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GPIOF_OUT_INIT_LOW, "NAND ALE"); |
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if (ret) |
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return ret; |
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ret = devm_gpio_request_one(info->dev, info->gpio_read, |
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GPIOF_OUT_INIT_LOW, "NAND READ"); |
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if (ret) |
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return ret; |
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ret = devm_gpio_request_one(info->dev, info->gpio_rdy, |
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GPIOF_IN, "NAND RDY"); |
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return ret; |
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} |
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static int rb91x_nand_probe(struct platform_device *pdev) |
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{ |
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struct rb91x_nand_info *info; |
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struct rb91x_nand_info *rbni; |
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struct rb91x_nand_platform_data *pdata; |
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int ret; |
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pr_info(DRV_DESC "\n"); |
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info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
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if (!info) |
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pdata = dev_get_platdata(&pdev->dev); |
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if (!pdata) |
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return -EINVAL; |
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rbni = devm_kzalloc(&pdev->dev, sizeof(*rbni), GFP_KERNEL); |
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if (!rbni) |
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return -ENOMEM; |
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info->chip.priv = &info; |
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info->mtd.priv = &info->chip; |
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info->mtd.owner = THIS_MODULE; |
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rbni->dev = &pdev->dev; |
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rbni->gpio_nce = pdata->gpio_nce; |
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rbni->gpio_ale = pdata->gpio_ale; |
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rbni->gpio_cle = pdata->gpio_cle; |
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rbni->gpio_read = pdata->gpio_read; |
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rbni->gpio_nrw = pdata->gpio_nrw; |
|
|
|
|
rbni->gpio_rdy = pdata->gpio_rdy; |
|
|
|
|
rbni->gpio_nle = pdata->gpio_nle; |
|
|
|
|
|
|
|
|
|
info->chip.cmd_ctrl = rb91x_nand_cmd_ctrl; |
|
|
|
|
info->chip.dev_ready = rb91x_nand_dev_ready; |
|
|
|
|
info->chip.read_byte = rb91x_nand_read_byte; |
|
|
|
|
info->chip.write_buf = rb91x_nand_write_buf; |
|
|
|
|
info->chip.read_buf = rb91x_nand_read_buf; |
|
|
|
|
rbni->chip.priv = &rbni; |
|
|
|
|
rbni->mtd.priv = &rbni->chip; |
|
|
|
|
rbni->mtd.owner = THIS_MODULE; |
|
|
|
|
|
|
|
|
|
info->chip.chip_delay = 25; |
|
|
|
|
info->chip.ecc.mode = NAND_ECC_SOFT; |
|
|
|
|
rbni->chip.cmd_ctrl = rb91x_nand_cmd_ctrl; |
|
|
|
|
rbni->chip.dev_ready = rb91x_nand_dev_ready; |
|
|
|
|
rbni->chip.read_byte = rb91x_nand_read_byte; |
|
|
|
|
rbni->chip.write_buf = rb91x_nand_write_buf; |
|
|
|
|
rbni->chip.read_buf = rb91x_nand_read_buf; |
|
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, info); |
|
|
|
|
rbni->chip.chip_delay = 25; |
|
|
|
|
rbni->chip.ecc.mode = NAND_ECC_SOFT; |
|
|
|
|
|
|
|
|
|
ret = nand_scan_ident(&info->mtd, 1, NULL); |
|
|
|
|
platform_set_drvdata(pdev, rbni); |
|
|
|
|
|
|
|
|
|
ret = rb91x_nand_gpio_init(rbni); |
|
|
|
|
if (ret) |
|
|
|
|
return ret; |
|
|
|
|
|
|
|
|
|
if (info->mtd.writesize == 512) |
|
|
|
|
info->chip.ecc.layout = &rb91x_nand_ecclayout; |
|
|
|
|
ret = nand_scan_ident(&rbni->mtd, 1, NULL); |
|
|
|
|
if (ret) |
|
|
|
|
return ret; |
|
|
|
|
|
|
|
|
|
if (rbni->mtd.writesize == 512) |
|
|
|
|
rbni->chip.ecc.layout = &rb91x_nand_ecclayout; |
|
|
|
|
|
|
|
|
|
ret = nand_scan_tail(&info->mtd); |
|
|
|
|
ret = nand_scan_tail(&rbni->mtd); |
|
|
|
|
if (ret) |
|
|
|
|
return ret; |
|
|
|
|
|
|
|
|
|
ret = mtd_device_register(&info->mtd, rb91x_nand_partitions, |
|
|
|
|
ret = mtd_device_register(&rbni->mtd, rb91x_nand_partitions, |
|
|
|
|
ARRAY_SIZE(rb91x_nand_partitions)); |
|
|
|
|
if (ret) |
|
|
|
|
goto err_release_nand; |
|
|
|
@ -325,7 +347,7 @@ static int rb91x_nand_probe(struct platform_device *pdev) |
|
|
|
|
return 0; |
|
|
|
|
|
|
|
|
|
err_release_nand: |
|
|
|
|
nand_release(&info->mtd); |
|
|
|
|
nand_release(&rbni->mtd); |
|
|
|
|
return ret; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
@ -342,7 +364,7 @@ static struct platform_driver rb91x_nand_driver = { |
|
|
|
|
.probe = rb91x_nand_probe, |
|
|
|
|
.remove = rb91x_nand_remove, |
|
|
|
|
.driver = { |
|
|
|
|
.name = DRV_NAME, |
|
|
|
|
.name = RB91X_NAND_DRIVER_NAME, |
|
|
|
|
.owner = THIS_MODULE, |
|
|
|
|
}, |
|
|
|
|
}; |
|
|
|
|