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@ -513,14 +513,16 @@ static void ag71xx_fast_reset(struct ag71xx *ag) |
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); |
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struct net_device *dev = ag->dev; |
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u32 reset_mask = pdata->reset_bit; |
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u32 rx_ds, tx_ds; |
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u32 rx_ds; |
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u32 mii_reg; |
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reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC; |
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ag71xx_hw_stop(ag); |
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wmb(); |
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mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); |
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rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); |
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tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC); |
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ath79_device_reset_set(reset_mask); |
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udelay(10); |
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@ -530,13 +532,16 @@ static void ag71xx_fast_reset(struct ag71xx *ag) |
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ag71xx_dma_reset(ag); |
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ag71xx_hw_setup(ag); |
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ag71xx_tx_packets(ag, true); |
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ag->tx_ring.curr = 0; |
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ag->tx_ring.dirty = 0; |
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netdev_reset_queue(ag->dev); |
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/* setup max frame length */ |
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ag71xx_wr(ag, AG71XX_REG_MAC_MFL, |
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ag71xx_max_frame_len(ag->dev->mtu)); |
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ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); |
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ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds); |
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ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); |
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ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); |
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ag71xx_hw_set_macaddr(ag, dev->dev_addr); |
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@ -962,6 +967,9 @@ static int ag71xx_tx_packets(struct ag71xx *ag, bool flush) |
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break; |
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} |
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if (flush) |
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desc->ctrl |= DESC_EMPTY; |
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n++; |
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if (!skb) |
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continue; |
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