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@ -22,7 +22,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. |
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -1158,6 +1158,10 @@ config SOC_AR934X
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@@ -1168,6 +1168,10 @@ config SOC_AR934X
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select PCI_AR724X if PCI
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def_bool n
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@ -33,7 +33,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. |
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config SOC_QCA955X
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select HW_HAS_PCI
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select PCI_AR724X if PCI
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@@ -1200,7 +1204,7 @@ config ATH79_DEV_USB
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@@ -1210,7 +1214,7 @@ config ATH79_DEV_USB
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def_bool n
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config ATH79_DEV_WMAC
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@ -233,11 +233,12 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. |
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else
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--- a/arch/mips/ath79/early_printk.c
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+++ b/arch/mips/ath79/early_printk.c
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@@ -114,6 +114,7 @@ static void prom_putchar_init(void)
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@@ -114,6 +114,8 @@ static void prom_putchar_init(void)
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case REV_ID_MAJOR_AR9341:
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case REV_ID_MAJOR_AR9342:
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case REV_ID_MAJOR_AR9344:
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+ case REV_ID_MAJOR_QCA9533:
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+ case REV_ID_MAJOR_QCA9533_V2:
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case REV_ID_MAJOR_QCA9556:
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case REV_ID_MAJOR_QCA9558:
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_prom_putchar = prom_putchar_ar71xx;
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@ -283,10 +284,22 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. |
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ath79_ip3_handler = ath79_default_ip3_handler;
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--- a/arch/mips/ath79/setup.c
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+++ b/arch/mips/ath79/setup.c
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@@ -151,6 +151,12 @@ static void __init ath79_detect_sys_type
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@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
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u32 major;
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u32 minor;
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u32 rev = 0;
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+ u32 ver = 1;
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id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
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major = id & REV_ID_MAJOR_MASK;
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@@ -151,6 +152,16 @@ static void __init ath79_detect_sys_type
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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+ case REV_ID_MAJOR_QCA9533_V2:
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+ ver = 2;
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+ /* drop through */
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+
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+ case REV_ID_MAJOR_QCA9533:
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+ ath79_soc = ATH79_SOC_QCA9533;
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+ chip = "9533";
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@ -296,15 +309,19 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. |
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case REV_ID_MAJOR_QCA9556:
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ath79_soc = ATH79_SOC_QCA9556;
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chip = "9556";
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@@ -169,7 +175,7 @@ static void __init ath79_detect_sys_type
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@@ -169,9 +180,9 @@ static void __init ath79_detect_sys_type
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ath79_soc_rev = rev;
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- if (soc_is_qca955x())
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- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
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- chip, rev);
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+ if (soc_is_qca953x() || soc_is_qca955x())
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sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
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chip, rev);
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+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
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+ chip, ver, rev);
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else
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sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
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pr_info("SoC: %s\n", ath79_sys_type);
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -105,6 +105,9 @@
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@ -381,15 +398,16 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. |
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#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
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#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
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@@ -565,6 +611,7 @@
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@@ -565,6 +611,8 @@
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#define REV_ID_MAJOR_AR9341 0x0120
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#define REV_ID_MAJOR_AR9342 0x1120
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#define REV_ID_MAJOR_AR9344 0x2120
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+#define REV_ID_MAJOR_QCA9533 0x0140
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+#define REV_ID_MAJOR_QCA9533_V2 0x0160
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#define REV_ID_MAJOR_QCA9556 0x0130
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#define REV_ID_MAJOR_QCA9558 0x1130
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@@ -587,6 +634,8 @@
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@@ -587,6 +635,8 @@
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#define AR934X_REV_ID_REVISION_MASK 0xf
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@ -398,7 +416,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. |
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#define QCA955X_REV_ID_REVISION_MASK 0xf
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/*
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@@ -640,6 +689,7 @@
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@@ -640,6 +690,7 @@
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#define AR913X_GPIO_COUNT 22
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#define AR933X_GPIO_COUNT 30
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#define AR934X_GPIO_COUNT 23
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