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@ -29,6 +29,7 @@ |
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#include <linux/interrupt.h> |
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#include <linux/ioport.h> |
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#include <asm/io.h> |
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#include <asm/irq.h> |
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#include <asm/irq_cpu.h> |
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#include <asm/mipsregs.h> |
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@ -37,18 +38,18 @@ |
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#include <asm/mach-adm5120/adm5120_defs.h> |
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#include <asm/mach-adm5120/adm5120_irq.h> |
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#define INTC_REG(r) (*(volatile u32 *)(KSEG1ADDR(ADM5120_INTC_BASE) + r)) |
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#define INTC_WRITE(reg, val) __raw_writel((val), \ |
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(void __iomem *)(KSEG1ADDR(ADM5120_INTC_BASE) + reg)) |
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#define INTC_READ(reg) __raw_readl( \ |
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(void __iomem *)(KSEG1ADDR(ADM5120_INTC_BASE) + reg)) |
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static void adm5120_intc_irq_unmask(unsigned int irq); |
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static void adm5120_intc_irq_mask(unsigned int irq); |
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static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type); |
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static struct irq_chip adm5120_intc_irq_chip = { |
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
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.name = "INTC", |
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#else |
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.typename = "INTC", |
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#endif |
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.unmask = adm5120_intc_irq_unmask, |
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.mask = adm5120_intc_irq_mask, |
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.mask_ack = adm5120_intc_irq_mask, |
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@ -62,22 +63,14 @@ static struct irqaction adm5120_intc_irq_action = { |
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static void adm5120_intc_irq_unmask(unsigned int irq) |
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{ |
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unsigned long flags; |
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irq -= ADM5120_INTC_IRQ_BASE; |
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local_irq_save(flags); |
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INTC_REG(INTC_REG_IRQ_ENABLE) = (1 << irq); |
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local_irq_restore(flags); |
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INTC_WRITE(INTC_REG_IRQ_ENABLE, 1 << irq); |
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} |
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static void adm5120_intc_irq_mask(unsigned int irq) |
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{ |
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unsigned long flags; |
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irq -= ADM5120_INTC_IRQ_BASE; |
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local_irq_save(flags); |
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INTC_REG(INTC_REG_IRQ_DISABLE) = (1 << irq); |
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local_irq_restore(flags); |
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INTC_WRITE(INTC_REG_IRQ_DISABLE, 1 << irq); |
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} |
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static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type) |
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@ -86,9 +79,8 @@ static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type) |
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#if 1 |
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unsigned int sense; |
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unsigned long mode; |
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int err; |
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int err = 0; |
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err = 0; |
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sense = flow_type & (IRQ_TYPE_SENSE_MASK); |
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switch (sense) { |
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case IRQ_TYPE_NONE: |
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@ -108,20 +100,20 @@ static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type) |
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err = -EINVAL; |
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break; |
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} |
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if (err) |
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return err; |
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switch (irq) { |
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case ADM5120_IRQ_GPIO2: |
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case ADM5120_IRQ_GPIO4: |
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mode = INTC_REG(INTC_REG_INT_MODE); |
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mode = INTC_READ(INTC_REG_INT_MODE); |
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if (sense == IRQ_TYPE_LEVEL_LOW) |
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mode |= (1 << (irq-ADM5120_INTC_IRQ_BASE)); |
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else |
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mode &= (1 << (irq-ADM5120_INTC_IRQ_BASE)); |
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INTC_REG(INTC_REG_INT_MODE) = mode; |
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INTC_WRITE(INTC_REG_INT_MODE, mode); |
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/* fallthrogh */ |
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default: |
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irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; |
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@ -137,33 +129,21 @@ static void adm5120_intc_irq_dispatch(void) |
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unsigned long status; |
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int irq; |
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#if 1 |
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/* dispatch only one IRQ at a time */ |
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status = INTC_REG(INTC_REG_IRQ_STATUS) & INTC_INT_ALL; |
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status = INTC_READ(INTC_REG_IRQ_STATUS) & INTC_INT_ALL; |
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if (status) { |
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irq = ADM5120_INTC_IRQ_BASE+fls(status)-1; |
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do_IRQ(irq); |
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} else |
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spurious_interrupt(); |
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#else |
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status = INTC_REG(INTC_REG_IRQ_STATUS) & INTC_INT_ALL; |
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if (status) { |
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for (irq=ADM5120_INTC_IRQ_BASE; irq <= ADM5120_INTC_IRQ_BASE + |
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INTC_IRQ_LAST; irq++, status >>=1) { |
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if ((status & 1) == 1) |
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do_IRQ(irq); |
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} |
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} else |
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spurious_interrupt(); |
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#endif |
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} |
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asmlinkage void plat_irq_dispatch(void) |
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{ |
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unsigned long pending; |
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pending = read_c0_status() & read_c0_cause(); |
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pending = read_c0_status() & read_c0_cause() & ST0_IM; |
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if (pending & STATUSF_IP7) |
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do_IRQ(ADM5120_IRQ_COUNTER); |
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@ -174,23 +154,24 @@ asmlinkage void plat_irq_dispatch(void) |
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} |
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#define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED) |
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static void __init adm5120_intc_irq_init(int base) |
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{ |
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int i; |
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/* disable all interrupts */ |
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INTC_REG(INTC_REG_IRQ_DISABLE) = INTC_INT_ALL; |
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INTC_WRITE(INTC_REG_IRQ_DISABLE, INTC_INT_ALL); |
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/* setup all interrupts to generate IRQ instead of FIQ */ |
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INTC_REG(INTC_REG_INT_MODE) = 0; |
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INTC_WRITE(INTC_REG_INT_MODE, 0); |
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/* set active level for all external interrupts to HIGH */ |
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INTC_REG(INTC_REG_INT_LEVEL) = 0; |
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INTC_WRITE(INTC_REG_INT_LEVEL, 0); |
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/* disable usage of the TEST_SOURCE register */ |
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INTC_REG(INTC_REG_IRQ_SOURCE_SELECT) = 0; |
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INTC_WRITE(INTC_REG_IRQ_SOURCE_SELECT, 0); |
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for(i=ADM5120_INTC_IRQ_BASE; i <= ADM5120_INTC_IRQ_BASE+INTC_IRQ_LAST; |
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for (i = ADM5120_INTC_IRQ_BASE; i <= ADM5120_INTC_IRQ_BASE+INTC_IRQ_LAST; |
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i++) { |
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irq_desc[i].status = INTC_IRQ_STATUS; |
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set_irq_chip_and_handler(i, &adm5120_intc_irq_chip,
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set_irq_chip_and_handler(i, &adm5120_intc_irq_chip, |
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handle_level_irq); |
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} |
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