From 128b623ec87d8f22412c40436a610e6a03517745 Mon Sep 17 00:00:00 2001 From: Nicolas Thill Date: Mon, 27 Apr 2009 11:20:36 +0000 Subject: [PATCH] gcc: fix 4.2.4 ICE on avr32 (see http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34762) SVN-Revision: 15434 --- .../gcc/patches/4.2.4/952-bug_34762.patch | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 toolchain/gcc/patches/4.2.4/952-bug_34762.patch diff --git a/toolchain/gcc/patches/4.2.4/952-bug_34762.patch b/toolchain/gcc/patches/4.2.4/952-bug_34762.patch new file mode 100644 index 0000000000..1ccd968d97 --- /dev/null +++ b/toolchain/gcc/patches/4.2.4/952-bug_34762.patch @@ -0,0 +1,49 @@ +http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34762 + +--- a/gcc/reload.c ++++ b/gcc/reload.c +@@ -4789,7 +4789,7 @@ find_reloads_address (enum machine_mode + find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), + &XEXP (tem, 0), opnum, + ADDR_TYPE (type), ind_levels, insn); +- if (tem != orig) ++ if (!rtx_equal_p (tem, orig)) + push_reg_equiv_alt_mem (regno, tem); + } + /* We can avoid a reload if the register's equivalent memory +@@ -5589,7 +5589,7 @@ find_reloads_address_1 (enum machine_mod + RELOAD_OTHER, + ind_levels, insn); + +- if (tem != orig) ++ if (!rtx_equal_p (tem, orig)) + push_reg_equiv_alt_mem (regno, tem); + + /* Then reload the memory location into a base +@@ -5656,7 +5656,7 @@ find_reloads_address_1 (enum machine_mod + find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), + &XEXP (tem, 0), opnum, type, + ind_levels, insn); +- if (tem != orig) ++ if (!rtx_equal_p (tem, orig)) + push_reg_equiv_alt_mem (regno, tem); + /* Put this inside a new increment-expression. */ + x = gen_rtx_fmt_e (GET_CODE (x), GET_MODE (x), tem); +@@ -5848,7 +5848,7 @@ find_reloads_address_1 (enum machine_mod + find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), + &XEXP (x, 0), opnum, ADDR_TYPE (type), + ind_levels, insn); +- if (x != tem) ++ if (!rtx_equal_p (x, tem)) + push_reg_equiv_alt_mem (regno, x); + } + } +@@ -6076,7 +6076,7 @@ find_reloads_subreg_address (rtx x, int + XEXP (tem, 0), &XEXP (tem, 0), + opnum, type, ind_levels, insn); + /* ??? Do we need to handle nonzero offsets somehow? */ +- if (!offset && tem != orig) ++ if (!offset && !rtx_equal_p (tem, orig)) + push_reg_equiv_alt_mem (regno, tem); + + /* For some processors an address may be valid in the