|
|
|
@ -742,12 +742,11 @@ ar8236_init_globals(struct ar8xxx_priv *priv) |
|
|
|
|
AR8316_GCTRL_MTU, 9018 + 8 + 2); |
|
|
|
|
|
|
|
|
|
/* enable cpu port to receive arp frames */ |
|
|
|
|
ar8xxx_rmw(priv, AR8216_REG_ATU_CTRL, |
|
|
|
|
AR8236_ATU_CTRL_RES, AR8236_ATU_CTRL_RES); |
|
|
|
|
ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL, |
|
|
|
|
AR8236_ATU_CTRL_RES); |
|
|
|
|
|
|
|
|
|
/* enable cpu port to receive multicast and broadcast frames */ |
|
|
|
|
ar8xxx_rmw(priv, AR8216_REG_FLOOD_MASK, |
|
|
|
|
AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN, |
|
|
|
|
ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK, |
|
|
|
|
AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN); |
|
|
|
|
|
|
|
|
|
/* Enable MIB counters */ |
|
|
|
@ -979,13 +978,11 @@ ar8216_set_mirror_regs(struct ar8xxx_priv *priv) |
|
|
|
|
(priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S)); |
|
|
|
|
|
|
|
|
|
if (priv->mirror_rx) |
|
|
|
|
ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port), |
|
|
|
|
AR8216_PORT_CTRL_MIRROR_RX, |
|
|
|
|
ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port), |
|
|
|
|
AR8216_PORT_CTRL_MIRROR_RX); |
|
|
|
|
|
|
|
|
|
if (priv->mirror_tx) |
|
|
|
|
ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port), |
|
|
|
|
AR8216_PORT_CTRL_MIRROR_TX, |
|
|
|
|
ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port), |
|
|
|
|
AR8216_PORT_CTRL_MIRROR_TX); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|