Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>master
Álvaro Fernández Rojas
8 years ago
parent
1da87516e5
commit
0aa6c7df60
@ -1,49 +0,0 @@ |
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From f1ba020af5076172c9d29006a747ccf40027fedc Mon Sep 17 00:00:00 2001
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Message-Id: <f1ba020af5076172c9d29006a747ccf40027fedc.1458840219.git.mschiffer@universe-factory.net>
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From: Matthias Schiffer <mschiffer@universe-factory.net>
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Date: Thu, 24 Mar 2016 15:34:05 +0100
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Subject: [PATCH] MIPS: ath79: make bootconsole wait for both THRE and TEMT
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This makes the ath79 bootconsole behave the same way as the generic 8250
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bootconsole.
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Also waiting for TEMT (transmit buffer is empty) instead of just THRE
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(transmit buffer is not full) ensures that all characters have been
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transmitted before the real serial driver starts reconfiguring the serial
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controller (which would sometimes result in garbage being transmitted.)
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This change does not cause a visible performance loss.
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In addition, this seems to fix a hang observed in certain configurations on
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many AR7xxx/AR9xxx SoCs during autoconfig of the real serial driver.
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A more complete follow-up patch will disable 8250 autoconfig for ath79
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altogether (the serial controller is detected as a 16550A, which is not
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fully compatible with the ath79 serial, and the autoconfig may lead to
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undefined behavior on ath79.)
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Cc: <stable@vger.kernel.org>
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Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
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---
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arch/mips/ath79/early_printk.c | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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--- a/arch/mips/ath79/early_printk.c
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+++ b/arch/mips/ath79/early_printk.c
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@@ -31,13 +31,15 @@ static inline void prom_putchar_wait(voi
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} while (1);
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}
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+#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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+
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static void prom_putchar_ar71xx(unsigned char ch)
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{
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void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
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- prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
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+ prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
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__raw_writel(ch, base + UART_TX * 4);
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- prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
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+ prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
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}
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static void prom_putchar_ar933x(unsigned char ch)
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@ -1,43 +0,0 @@ |
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From 4d4b769727386c6a1b7274e3083cc6b24364b4fa Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Mon, 29 Feb 2016 11:39:17 +0000
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Subject: [PATCH 256/381] clk: bcm2835: pll_off should only update
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CM_PLL_ANARST
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bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
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register, which may lose the other bits that are currently set by the
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clock dividers.
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It also now locks during the read/modify/write cycle of both
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registers.
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Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
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audio domain clocks")
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 6727f086cfe4ddcc651eb2bf4301abfcf619be06)
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---
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drivers/clk/bcm/clk-bcm2835.c | 10 ++++++++--
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1 file changed, 8 insertions(+), 2 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -913,8 +913,14 @@ static void bcm2835_pll_off(struct clk_h
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struct bcm2835_cprman *cprman = pll->cprman;
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const struct bcm2835_pll_data *data = pll->data;
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- cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
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- cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN);
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+ spin_lock(&cprman->regs_lock);
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+ cprman_write(cprman, data->cm_ctrl_reg,
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+ cprman_read(cprman, data->cm_ctrl_reg) |
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+ CM_PLL_ANARST);
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+ cprman_write(cprman, data->a2w_ctrl_reg,
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+ cprman_read(cprman, data->a2w_ctrl_reg) |
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+ A2W_PLL_CTRL_PWRDN);
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+ spin_unlock(&cprman->regs_lock);
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}
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static int bcm2835_pll_on(struct clk_hw *hw)
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@ -1,36 +0,0 @@ |
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From 260572944700ab13fa3f7a68a387556220cef277 Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Mon, 29 Feb 2016 11:39:20 +0000
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Subject: [PATCH 257/381] clk: bcm2835: divider value has to be 1 or more
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Current clamping of a normal divider allows a value < 1 to be valid.
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A divider of < 1 would actually only be possible if we had a PLL...
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So this patch clamps the divider to 1.
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Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
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audio domain clocks")
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 997f16bd5d2e9b3456027f96fcadfe1e2bf12f4e)
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---
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drivers/clk/bcm/clk-bcm2835.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1202,8 +1202,9 @@ static u32 bcm2835_clock_choose_div(stru
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div += unused_frac_mask + 1;
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div &= ~unused_frac_mask;
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- /* Clamp to the limits. */
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- div = max(div, unused_frac_mask + 1);
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+ /* clamp to min divider of 1 */
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+ div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS);
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+ /* clamp to the highest possible fractional divider */
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div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
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CM_DIV_FRAC_BITS - data->frac_bits));
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@ -1,58 +0,0 @@ |
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Some of the GPIO configs were wrong in the submitted DTS files,
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this patch fixes all affected boards.
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Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
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Cc: <stable@vger.kernel.org> # v4.1 +
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---
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arch/arm/boot/dts/armada-385-linksys.dtsi | 6 +++---
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arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 4 ++--
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2 files changed, 5 insertions(+), 5 deletions(-)
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--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
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+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
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@@ -245,7 +245,7 @@
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button@2 {
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label = "Factory Reset Button";
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linux,code = <KEY_RESTART>;
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- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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+ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
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};
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};
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@@ -260,7 +260,7 @@
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};
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sata {
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- gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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+ gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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};
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@@ -313,7 +313,7 @@
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&pinctrl {
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keys_pin: keys-pin {
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- marvell,pins = "mpp24", "mpp47";
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+ marvell,pins = "mpp24", "mpp29";
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marvell,function = "gpio";
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};
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--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
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+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
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@@ -304,13 +304,13 @@
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button@1 {
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label = "WPS";
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linux,code = <KEY_WPS_BUTTON>;
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- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
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};
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button@2 {
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label = "Factory Reset Button";
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linux,code = <KEY_RESTART>;
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- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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+ gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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};
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};
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