parent
976f690ebd
commit
08bd604941
@ -0,0 +1,604 @@ |
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/*
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* SPI driver for the Vitesse VSC7385 ethernet switch |
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* |
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> |
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* |
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* Parts of this file are based on Atheros' 2.6.15 BSP |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 as published |
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* by the Free Software Foundation. |
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*/ |
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#include <linux/types.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/bitops.h> |
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#include <linux/firmware.h> |
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#include <linux/spi/spi.h> |
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#include <linux/spi/vsc7385.h> |
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#define DRV_NAME "spi-vsc7385" |
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#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver" |
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#define DRV_VERSION "0.1.0" |
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#define VSC73XX_BLOCK_MAC 0x1 |
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#define VSC73XX_BLOCK_2 0x2 |
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#define VSC73XX_BLOCK_MII 0x3 |
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#define VSC73XX_BLOCK_4 0x4 |
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#define VSC73XX_BLOCK_5 0x5 |
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#define VSC73XX_BLOCK_SYSTEM 0x7 |
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#define VSC73XX_SUBBLOCK_PORT_0 0 |
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#define VSC73XX_SUBBLOCK_PORT_1 1 |
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#define VSC73XX_SUBBLOCK_PORT_2 2 |
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#define VSC73XX_SUBBLOCK_PORT_3 3 |
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#define VSC73XX_SUBBLOCK_PORT_4 4 |
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#define VSC73XX_SUBBLOCK_PORT_MAC 6 |
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/* MAC Block registers */ |
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#define VSC73XX_MAC_CFG 0x0 |
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#define VSC73XX_ADVPORTM 0x19 |
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#define VSC73XX_RXOCT 0x50 |
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#define VSC73XX_TXOCT 0x51 |
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#define VSC73XX_C_RX0 0x52 |
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#define VSC73XX_C_RX1 0x53 |
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#define VSC73XX_C_RX2 0x54 |
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#define VSC73XX_C_TX0 0x55 |
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#define VSC73XX_C_TX1 0x56 |
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#define VSC73XX_C_TX2 0x57 |
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#define VSC73XX_C_CFG 0x58 |
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/* MAC_CFG register bits */ |
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#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31) |
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#define VSC73XX_MAC_CFG_PORT_RST (1 << 29) |
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#define VSC73XX_MAC_CFG_TX_EN (1 << 28) |
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#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27) |
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#define VSC73XX_MAC_CFG_FDX (1 << 18) |
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#define VSC73XX_MAC_CFG_GIGE (1 << 17) |
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#define VSC73XX_MAC_CFG_RX_EN (1 << 16) |
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#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15) |
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#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14) |
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#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13) |
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#define VSC73XX_MAC_CFG_TX_IPG(x) ((x & 0x1f) << 6) |
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#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5) |
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#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4) |
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#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x & 0x3) << 0) |
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/* ADVPORTM register bits */ |
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#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7) |
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#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6) |
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#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5) |
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#define VSC73XX_ADVPORTM_INV_GTX (1 << 4) |
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#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3) |
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#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2) |
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#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1) |
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#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0) |
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/* MII Block registers */ |
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#define VSC73XX_MII_STAT 0x0 |
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#define VSC73XX_MII_CMD 0x1 |
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#define VSC73XX_MII_DATA 0x2 |
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/* System Block registers */ |
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#define VSC73XX_ICPU_SIPAD 0x01 |
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#define VSC73XX_ICPU_CLOCK_DELAY 0x05 |
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#define VSC73XX_ICPU_CTRL 0x10 |
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#define VSC73XX_ICPU_ADDR 0x11 |
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#define VSC73XX_ICPU_SRAM 0x12 |
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#define VSC73XX_ICPU_MBOX_VAL 0x15 |
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#define VSC73XX_ICPU_MBOX_SET 0x16 |
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#define VSC73XX_ICPU_MBOX_CLR 0x17 |
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#define VSC73XX_ICPU_CHIPID 0x18 |
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#define VSC73XX_ICPU_GPIO 0x34 |
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#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8) |
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#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7) |
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#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3) |
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#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2) |
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#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1) |
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#define VSC73XX_ICPU_CTRL_SRST (1 << 0) |
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#define VSC73XX_CMD_MODE_READ 0 |
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#define VSC73XX_CMD_MODE_WRITE 1 |
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#define VSC73XX_CMD_MODE_SHIFT 4 |
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#define VSC73XX_CMD_BLOCK_SHIFT 5 |
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#define VSC73XX_CMD_BLOCK_MASK 0x7 |
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#define VSC73XX_CMD_SUBBLOCK_MASK 0xf |
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#define VSC7385_CLOCK_DELAY ((3 << 4) | 3) |
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#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) |
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#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ |
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VSC73XX_ICPU_CTRL_BOOT_EN | \
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VSC73XX_ICPU_CTRL_EXT_ACC_EN) |
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#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ |
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VSC73XX_ICPU_CTRL_BOOT_EN | \
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VSC73XX_ICPU_CTRL_CLK_EN | \
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VSC73XX_ICPU_CTRL_SRST) |
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#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \ |
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VSC73XX_ADVPORTM_EXC_COL_CONT | \
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VSC73XX_ADVPORTM_EXT_PORT | \
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VSC73XX_ADVPORTM_INV_GTX | \
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VSC73XX_ADVPORTM_ENA_GTX | \
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VSC73XX_ADVPORTM_DDR_MODE | \
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VSC73XX_ADVPORTM_IO_LOOPBACK | \
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VSC73XX_ADVPORTM_HOST_LOOPBACK) |
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#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \ |
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VSC73XX_ADVPORTM_ENA_GTX | \
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VSC73XX_ADVPORTM_DDR_MODE) |
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#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ |
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VSC73XX_MAC_CFG_MAC_RX_RST | \
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VSC73XX_MAC_CFG_MAC_TX_RST) |
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#define VSC7385_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \ |
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VSC73XX_MAC_CFG_FDX | \
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VSC73XX_MAC_CFG_GIGE | \
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VSC73XX_MAC_CFG_RX_EN | \
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VSC73XX_MAC_CFG_TX_IPG(6) | \
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4) |
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#define VSC73XX_RESET_DELAY 100 |
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struct vsc7385 { |
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struct spi_device *spi; |
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struct mutex lock; |
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struct vsc7385_platform_data *pdata; |
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}; |
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static int vsc7385_is_addr_valid(u8 block, u8 subblock) |
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{ |
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switch (block) { |
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case VSC73XX_BLOCK_MAC: |
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switch (subblock) { |
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case 0 ... 4: |
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case 6: |
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return 1; |
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} |
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break; |
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case VSC73XX_BLOCK_2: |
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case VSC73XX_BLOCK_SYSTEM: |
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switch (subblock) { |
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case 0: |
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return 1; |
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} |
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break; |
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case VSC73XX_BLOCK_MII: |
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case VSC73XX_BLOCK_4: |
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case VSC73XX_BLOCK_5: |
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switch (subblock) { |
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case 0 ... 1: |
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return 1; |
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} |
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break; |
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} |
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return 0; |
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} |
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static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock) |
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{ |
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u8 ret; |
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ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT; |
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ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT; |
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ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK; |
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return ret; |
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} |
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static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, |
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u32 *value) |
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{ |
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u8 cmd[4]; |
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u8 buf[4]; |
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struct spi_transfer t[2]; |
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struct spi_message m; |
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int err; |
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if (!vsc7385_is_addr_valid(block, subblock)) |
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return -EINVAL; |
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spi_message_init(&m); |
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memset(&t, 0, sizeof(t)); |
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t[0].tx_buf = cmd; |
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t[0].len = sizeof(cmd); |
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spi_message_add_tail(&t[0], &m); |
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t[1].rx_buf = buf; |
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t[1].len = sizeof(buf); |
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spi_message_add_tail(&t[1], &m); |
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cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock); |
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cmd[1] = reg; |
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cmd[2] = 0; |
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cmd[3] = 0; |
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mutex_lock(&vsc->lock); |
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err = spi_sync(vsc->spi, &m); |
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mutex_unlock(&vsc->lock); |
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if (err) |
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return err; |
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*value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) | |
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(((u32) buf[2]) << 8) | ((u32) buf[3]); |
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return 0; |
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} |
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static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, |
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u32 value) |
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{ |
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u8 cmd[2]; |
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u8 buf[4]; |
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struct spi_transfer t[2]; |
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struct spi_message m; |
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int err; |
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if (!vsc7385_is_addr_valid(block, subblock)) |
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return -EINVAL; |
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spi_message_init(&m); |
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memset(&t, 0, sizeof(t)); |
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t[0].tx_buf = cmd; |
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t[0].len = sizeof(cmd); |
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spi_message_add_tail(&t[0], &m); |
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t[1].tx_buf = buf; |
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t[1].len = sizeof(buf); |
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spi_message_add_tail(&t[1], &m); |
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cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock); |
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cmd[1] = reg; |
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buf[0] = (value >> 24) & 0xff; |
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buf[1] = (value >> 16) & 0xff; |
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buf[2] = (value >> 8) & 0xff; |
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buf[3] = value & 0xff; |
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mutex_lock(&vsc->lock); |
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err = spi_sync(vsc->spi, &m); |
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mutex_unlock(&vsc->lock); |
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return err; |
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} |
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static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block, |
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u8 subblock, u8 reg, u32 value, |
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u32 read_mask, u32 read_val) |
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{ |
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struct spi_device *spi = vsc->spi; |
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u32 t; |
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int err; |
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err = vsc7385_write(vsc, block, subblock, reg, value); |
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if (err) |
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return err; |
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err = vsc7385_read(vsc, block, subblock, reg, &t); |
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if (err) |
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return err; |
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if ((t & read_mask) != read_val) { |
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dev_err(&spi->dev, "register write error\n"); |
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return -EIO; |
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} |
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return 0; |
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} |
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static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val) |
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{ |
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return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, |
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VSC73XX_ICPU_CLOCK_DELAY, val); |
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} |
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static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val) |
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{ |
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return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, |
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VSC73XX_ICPU_CLOCK_DELAY, val); |
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} |
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static inline int vsc7385_icpu_stop(struct vsc7385 *vsc) |
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{ |
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return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, |
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VSC73XX_ICPU_CTRL_STOP); |
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} |
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static inline int vsc7385_icpu_start(struct vsc7385 *vsc) |
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{ |
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return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, |
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VSC73XX_ICPU_CTRL_START); |
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} |
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static inline int vsc7385_icpu_reset(struct vsc7385 *vsc) |
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{ |
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int rc; |
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rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR, |
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0x0000); |
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if (rc) |
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dev_err(&vsc->spi->dev, |
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"could not reset microcode, err=%d\n", rc); |
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return rc; |
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} |
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static int vsc7385_upload_ucode(struct vsc7385 *vsc) |
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{ |
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struct spi_device *spi = vsc->spi; |
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const struct firmware *firmware; |
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char *ucode_name; |
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unsigned char *dp; |
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unsigned int curVal; |
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int i; |
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int diffs; |
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int rc; |
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ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name |
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: "vsc7385_ucode.bin"; |
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rc = request_firmware(&firmware, ucode_name, &spi->dev); |
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if (rc) { |
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dev_err(&spi->dev, "request_firmware failed, err=%d\n", |
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rc); |
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return rc; |
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} |
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rc = vsc7385_icpu_stop(vsc); |
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if (rc) |
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goto out; |
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rc = vsc7385_icpu_reset(vsc); |
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if (rc) |
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goto out; |
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dev_info(&spi->dev, "uploading microcode...\n"); |
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dp = (unsigned char *) firmware->data; |
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for (i = 0; i < firmware->size; i++) { |
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rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, |
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VSC73XX_ICPU_SRAM, *dp++); |
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if (rc) { |
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dev_err(&spi->dev, "could not load microcode, err=%d\n", |
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rc); |
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goto out; |
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} |
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} |
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rc = vsc7385_icpu_reset(vsc); |
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if (rc) |
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goto out; |
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dev_info(&spi->dev, "verifying microcode...\n"); |
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dp = (unsigned char *) firmware->data; |
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diffs = 0; |
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for (i = 0; i < firmware->size; i++) { |
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rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, |
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VSC73XX_ICPU_SRAM, &curVal); |
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if (rc) { |
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dev_err(&spi->dev, "could not read microcode %d\n",rc); |
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goto out; |
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} |
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if (curVal > 0xff) { |
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dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n", |
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i, *dp, curVal); |
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rc = -EIO; |
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goto out; |
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} |
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if ((curVal & 0xff) != *dp) { |
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diffs++; |
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dev_err(&spi->dev, "verify error: %04x : %02x %02x\n", |
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i, *dp, curVal); |
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if (diffs > 4) |
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break; |
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} |
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dp++; |
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} |
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if (diffs) { |
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dev_err(&spi->dev, "microcode verification failed\n"); |
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rc = -EIO; |
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goto out; |
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} |
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dev_info(&spi->dev, "microcode uploaded\n"); |
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rc = vsc7385_icpu_start(vsc); |
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out: |
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release_firmware(firmware); |
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return rc; |
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} |
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static int vsc7385_setup(struct vsc7385 *vsc) |
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{ |
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int err; |
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err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0, |
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VSC73XX_ICPU_CLOCK_DELAY, |
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VSC7385_CLOCK_DELAY, |
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VSC7385_CLOCK_DELAY_MASK, |
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VSC7385_CLOCK_DELAY); |
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if (err) |
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goto err; |
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err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC, |
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VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM, |
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VSC7385_ADVPORTM_INIT, |
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VSC7385_ADVPORTM_MASK, |
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VSC7385_ADVPORTM_INIT); |
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if (err) |
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goto err; |
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err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, |
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VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET); |
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if (err) |
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goto err; |
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err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, |
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VSC73XX_MAC_CFG, VSC7385_MAC_CFG_INIT); |
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if (err) |
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goto err; |
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return 0; |
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err: |
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return err; |
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} |
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static int vsc7385_detect(struct vsc7385 *vsc) |
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{ |
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struct spi_device *spi = vsc->spi; |
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u32 t; |
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u32 id; |
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u32 rev; |
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int err; |
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err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, |
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VSC73XX_ICPU_MBOX_VAL, &t); |
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if (err) { |
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dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err); |
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return err; |
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} |
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if (t == 0xffffffff) { |
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dev_dbg(&spi->dev, "assert chip reset\n"); |
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if (vsc->pdata->reset) |
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vsc->pdata->reset(); |
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} |
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err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, |
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VSC73XX_ICPU_CHIPID, &t); |
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if (err) { |
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dev_err(&spi->dev, "unable to read chip id, err=%d\n", err); |
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return err; |
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} |
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|
||||
id = (t >> 12) & 0xffff; |
||||
switch (id) { |
||||
case 0x7385: |
||||
break; |
||||
default: |
||||
dev_err(&spi->dev, "unsupported chip, id=%04x\n", id); |
||||
return -ENODEV; |
||||
} |
||||
|
||||
rev = (t >> 28) & 0xf; |
||||
dev_info(&spi->dev, "VSC%04X (rev. %d) switch found \n", id, rev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int __devinit vsc7385_probe(struct spi_device *spi) |
||||
{ |
||||
struct vsc7385 *vsc; |
||||
struct vsc7385_platform_data *pdata; |
||||
int err; |
||||
|
||||
printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n"); |
||||
|
||||
pdata = spi->dev.platform_data; |
||||
if (!pdata) { |
||||
dev_err(&spi->dev, "no platform data specified\n"); |
||||
return-ENODEV; |
||||
} |
||||
|
||||
vsc = kzalloc(sizeof(*vsc), GFP_KERNEL); |
||||
if (!vsc) { |
||||
dev_err(&spi->dev, "no memory for private data\n"); |
||||
return-ENOMEM; |
||||
} |
||||
|
||||
mutex_init(&vsc->lock); |
||||
vsc->pdata = pdata; |
||||
vsc->spi = spi_dev_get(spi); |
||||
dev_set_drvdata(&spi->dev, vsc); |
||||
|
||||
spi->mode = SPI_MODE_0; |
||||
spi->bits_per_word = 8; |
||||
err = spi_setup(spi); |
||||
if (err) { |
||||
dev_err(&spi->dev, "spi_setup failed, err=%d \n", err); |
||||
goto err_drvdata; |
||||
} |
||||
|
||||
err = vsc7385_detect(vsc); |
||||
if (err) { |
||||
dev_err(&spi->dev, "no chip found, err=%d \n", err); |
||||
goto err_drvdata; |
||||
} |
||||
|
||||
err = vsc7385_upload_ucode(vsc); |
||||
if (err) |
||||
goto err_drvdata; |
||||
|
||||
err = vsc7385_setup(vsc); |
||||
if (err) |
||||
goto err_drvdata; |
||||
|
||||
return 0; |
||||
|
||||
err_drvdata: |
||||
dev_set_drvdata(&spi->dev, NULL); |
||||
kfree(vsc); |
||||
return err; |
||||
} |
||||
|
||||
static int __devexit vsc7385_remove(struct spi_device *spi) |
||||
{ |
||||
struct vsc7385_data *vsc; |
||||
|
||||
vsc = dev_get_drvdata(&spi->dev); |
||||
dev_set_drvdata(&spi->dev, NULL); |
||||
kfree(vsc); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct spi_driver vsc7385_driver = { |
||||
.driver = { |
||||
.name = DRV_NAME, |
||||
.bus = &spi_bus_type, |
||||
.owner = THIS_MODULE, |
||||
}, |
||||
.probe = vsc7385_probe, |
||||
.remove = __devexit_p(vsc7385_remove), |
||||
}; |
||||
|
||||
static int __init vsc7385_init(void) |
||||
{ |
||||
return spi_register_driver(&vsc7385_driver); |
||||
} |
||||
module_init(vsc7385_init); |
||||
|
||||
static void __exit vsc7385_exit(void) |
||||
{ |
||||
spi_unregister_driver(&vsc7385_driver); |
||||
} |
||||
module_exit(vsc7385_exit); |
||||
|
||||
MODULE_DESCRIPTION(DRV_DESC); |
||||
MODULE_VERSION(DRV_VERSION); |
||||
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); |
||||
MODULE_LICENSE("GPL v2"); |
||||
|
@ -0,0 +1,24 @@ |
||||
--- a/drivers/spi/Kconfig
|
||||
+++ b/drivers/spi/Kconfig
|
||||
@@ -272,6 +272,11 @@ config SPI_TLE62X0
|
||||
sysfs interface, with each line presented as a kind of GPIO
|
||||
exposing both switch control and diagnostic feedback.
|
||||
|
||||
+config SPI_VSC7385
|
||||
+ tristate "Vitesse VSC7385 ethernet switch driver"
|
||||
+ help
|
||||
+ SPI driver for the Vitesse VSC7385 ethernet switch.
|
||||
+
|
||||
#
|
||||
# Add new SPI protocol masters in alphabetical order above this line
|
||||
#
|
||||
--- a/drivers/spi/Makefile
|
||||
+++ b/drivers/spi/Makefile
|
||||
@@ -37,6 +37,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.
|
||||
|
||||
# SPI protocol drivers (device/link on bus)
|
||||
obj-$(CONFIG_SPI_SPIDEV) += spidev.o
|
||||
+obj-$(CONFIG_SPI_VSC7385) += spi_vsc7385.o
|
||||
obj-$(CONFIG_SPI_TLE62X0) += tle62x0.o
|
||||
# ... add above this line ...
|
||||
|
Loading…
Reference in new issue