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a8d3dc4d94
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022ac5019d
@ -0,0 +1,249 @@ |
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/*
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* Support for IBM PPC 405EP-based MagicBox board
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* Copyright (C) 2006 Karol Lewandowski |
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* |
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* Heavily based on bubinga.c |
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* |
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* Author: SAW (IBM), derived from walnut.c. |
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* Maintained by MontaVista Software <source@mvista.com> |
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* |
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* 2003 (c) MontaVista Softare Inc. This file is licensed under the |
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* terms of the GNU General Public License version 2. This program is |
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* licensed "as is" without any warranty of any kind, whether express |
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* or implied. |
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*/ |
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|
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#include <linux/autoconf.h> |
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#include <linux/init.h> |
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#include <linux/smp.h> |
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#include <linux/threads.h> |
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#include <linux/param.h> |
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#include <linux/string.h> |
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#include <linux/blkdev.h> |
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#include <linux/pci.h> |
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#include <linux/tty.h> |
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#include <linux/serial.h> |
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#include <linux/serial_core.h> |
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#include <asm/system.h> |
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#include <asm/pci-bridge.h> |
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#include <asm/processor.h> |
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#include <asm/machdep.h> |
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#include <asm/page.h> |
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#include <asm/time.h> |
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#include <asm/io.h> |
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#include <asm/kgdb.h> |
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#include <asm/ocp.h> |
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#include <asm/ibm_ocp_pci.h> |
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#include <platforms/4xx/ibm405ep.h> |
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#undef DEBUG |
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#ifdef DEBUG |
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#define DBG(x...) printk(x) |
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#else |
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#define DBG(x...) |
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#endif |
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extern bd_t __res; |
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/* Some IRQs unique to board
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* Used by the generic 405 PCI setup functions in ppc4xx_pci.c |
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*/ |
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int __init |
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ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) |
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{ |
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static char pci_irq_table[][4] = |
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/*
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* PCI IDSEL/INTPIN->INTLINE |
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* A B C D |
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*/ |
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{ |
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{28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */ |
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{29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */ |
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{30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */ |
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{31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */ |
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}; |
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const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; |
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return PCI_IRQ_TABLE_LOOKUP; |
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}; |
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/* The serial clock for the chip is an internal clock determined by
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* different clock speeds/dividers. |
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* Calculate the proper input baud rate and setup the serial driver. |
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*/ |
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static void __init |
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magicbox_early_serial_map(void) |
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{ |
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u32 uart_div; |
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int uart_clock; |
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struct uart_port port; |
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/* Calculate the serial clock input frequency
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* |
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* The base baud is the PLL OUTA (provided in the board info |
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* structure) divided by the external UART Divisor, divided |
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* by 16. |
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*/ |
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uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV); |
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uart_clock = __res.bi_procfreq / uart_div; |
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/* Setup serial port access */ |
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memset(&port, 0, sizeof(port)); |
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port.membase = (void*)ACTING_UART0_IO_BASE; |
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port.irq = ACTING_UART0_INT; |
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port.uartclk = uart_clock; |
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port.regshift = 0; |
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port.iotype = SERIAL_IO_MEM; |
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port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; |
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port.line = 0; |
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if (early_serial_setup(&port) != 0) { |
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printk("Early serial init of port 0 failed\n"); |
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} |
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port.membase = (void*)ACTING_UART1_IO_BASE; |
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port.irq = ACTING_UART1_INT; |
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port.line = 1; |
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if (early_serial_setup(&port) != 0) { |
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printk("Early serial init of port 1 failed\n"); |
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} |
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} |
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void __init |
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bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) |
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{ |
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unsigned int bar_response, bar; |
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/*
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* Expected PCI mapping: |
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* |
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* PLB addr PCI memory addr |
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* --------------------- --------------------- |
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* 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff |
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* 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff |
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* |
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* PLB addr PCI io addr |
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* --------------------- --------------------- |
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* e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000 |
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* |
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* The following code is simplified by assuming that the bootrom |
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* has been well behaved in following this mapping. |
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*/ |
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#ifdef DEBUG |
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int i; |
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printk("ioremap PCLIO_BASE = 0x%x\n", pcip); |
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printk("PCI bridge regs before fixup \n"); |
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for (i = 0; i <= 3; i++) { |
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); |
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); |
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); |
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); |
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} |
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printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); |
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printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); |
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printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); |
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printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); |
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#endif |
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/* added for IBM boot rom version 1.15 bios bar changes -AK */ |
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/* Disable region first */ |
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out_le32((void *) &(pcip->pmm[0].ma), 0x00000000); |
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/* PLB starting addr, PCI: 0x80000000 */ |
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out_le32((void *) &(pcip->pmm[0].la), 0x80000000); |
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/* PCI start addr, 0x80000000 */ |
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out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE); |
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/* 512MB range of PLB to PCI */ |
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out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000); |
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/* Enable no pre-fetch, enable region */ |
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out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff - |
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(PPC405_PCI_UPPER_MEM - |
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PPC405_PCI_MEM_BASE)) | 0x01)); |
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/* Disable region one */ |
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out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); |
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out_le32((void *) &(pcip->pmm[1].la), 0x00000000); |
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out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); |
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out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); |
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out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); |
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out_le32((void *) &(pcip->ptm1ms), 0x00000001); |
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/* Disable region two */ |
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out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); |
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out_le32((void *) &(pcip->pmm[2].la), 0x00000000); |
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out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); |
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out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); |
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out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); |
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out_le32((void *) &(pcip->ptm2ms), 0x00000000); |
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out_le32((void *) &(pcip->ptm2la), 0x00000000); |
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/* Zero config bars */ |
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for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { |
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early_write_config_dword(hose, hose->first_busno, |
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PCI_FUNC(hose->first_busno), bar, |
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0x00000000); |
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early_read_config_dword(hose, hose->first_busno, |
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PCI_FUNC(hose->first_busno), bar, |
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&bar_response); |
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DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", |
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hose->first_busno, PCI_SLOT(hose->first_busno), |
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PCI_FUNC(hose->first_busno), bar, bar_response); |
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} |
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/* end work arround */ |
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#ifdef DEBUG |
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printk("PCI bridge regs after fixup \n"); |
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for (i = 0; i <= 3; i++) { |
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); |
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); |
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); |
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); |
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} |
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printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); |
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printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); |
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printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); |
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printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); |
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#endif /* DEBUG */ |
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} |
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void __init |
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magicbox_setup_arch(void) |
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{ |
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ppc4xx_setup_arch(); |
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ibm_ocp_set_emac(0, 1); |
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magicbox_early_serial_map(); |
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/* Identify the system */ |
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printk("MagicBox port (C) 2005 Karol Lewandowski <kl@jasmine.eu.org>\n"); |
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} |
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void __init |
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magicbox_map_io(void) |
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{ |
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ppc4xx_map_io(); |
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} |
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void __init |
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5, |
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unsigned long r6, unsigned long r7) |
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{ |
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ppc4xx_init(r3, r4, r5, r6, r7); |
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ppc_md.setup_arch = magicbox_setup_arch; |
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ppc_md.setup_io_mappings = magicbox_map_io; |
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#ifdef CONFIG_KGDB |
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ppc_md.early_serial_map = bubinga_early_serial_map; |
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#endif |
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} |
@ -0,0 +1,47 @@ |
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/*
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* Support for IBM PPC 405EP-based MagicBox board |
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* |
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* Heavily based on bubinga.h |
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* |
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* |
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* Author: SAW (IBM), derived from walnut.h. |
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* Maintained by MontaVista Software <source@mvista.com> |
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* |
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* 2003 (c) MontaVista Softare Inc. This file is licensed under the |
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* terms of the GNU General Public License version 2. This program is |
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* licensed "as is" without any warranty of any kind, whether express |
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* or implied. |
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*/ |
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#ifdef __KERNEL__ |
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#ifndef __MAGICBOX_H__ |
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#define __MAGICBOX_H__ |
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#include <linux/autoconf.h> |
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#include <platforms/4xx/ibm405ep.h> |
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#include <asm/ppcboot.h> |
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/* Memory map for the "MagicBox" 405EP evaluation board -- generic 4xx. */ |
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/* The UART clock is based off an internal clock -
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* define BASE_BAUD based on the internal clock and divider(s). |
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* Since BASE_BAUD must be a constant, we will initialize it |
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* using clock/divider values which OpenBIOS initializes |
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* for typical configurations at various CPU speeds. |
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* The base baud is calculated as (FWDA / EXT UART DIV / 16) |
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*/ |
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#define BASE_BAUD 0 |
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/* Flash */ |
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#define PPC40x_FPGA_BASE 0xF0300000 |
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#define PPC40x_FPGA_REG_OFFS 1 /* offset to flash map reg */ |
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#define PPC40x_FLASH_ONBD_N(x) (x & 0x02) |
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#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01) |
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#define PPC40x_FLASH_LOW 0xFFF00000 |
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#define PPC40x_FLASH_HIGH 0xFFF80000 |
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#define PPC40x_FLASH_SIZE 0x80000 |
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#define PPC4xx_MACHINE_NAME "MagicBox" |
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#endif /* __MAGICBOX_H__ */ |
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#endif /* __KERNEL__ */ |
@ -0,0 +1,147 @@ |
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/* Driver for MagicBox 2.0 onboard CompactFlash adapter.
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* Written by Wojtek Kaniewski <wojtekka@toxygen.net> |
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* |
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* GNU General Public License. |
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*/ |
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#include <linux/types.h> |
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#include <linux/mm.h> |
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#include <linux/interrupt.h> |
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#include <linux/blkdev.h> |
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#include <linux/hdreg.h> |
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#include <linux/ide.h> |
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#include <linux/delay.h> |
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#include <linux/platform_device.h> |
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#define UIC0_PR 0xc4 |
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#define UIC0_TR 0xc5 |
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#define IRQ 25 |
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static int ide_offsets[IDE_NR_PORTS] = {0, 2, 4, 6, 8, 10, 12, 14, -1, -1}; |
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static u8 magicbox_ide_inb (unsigned long port) |
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{ |
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return (u8) (readw((void __iomem *) port) >> 8) & 255; |
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} |
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static u16 magicbox_ide_inw (unsigned long port) |
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{ |
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return (u16) readw((void __iomem *) port); |
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} |
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static void magicbox_ide_insw (unsigned long port, void *addr, u32 count) |
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{ |
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u16 *ptr; |
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for (ptr = addr; count--; ptr++) |
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*ptr = readw((void __iomem *) port); |
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} |
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static u32 magicbox_ide_inl (unsigned long port) |
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{ |
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return (u32) readl((void __iomem *) port); |
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} |
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static void magicbox_ide_insl (unsigned long port, void *addr, u32 count) |
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{ |
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u32 *ptr; |
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for (ptr = addr; count--; ptr++) |
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*ptr = readl((void __iomem *) port); |
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} |
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static void magicbox_ide_outb (u8 value, unsigned long port) |
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{ |
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writew(value << 8, (void __iomem *) port); |
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} |
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static void magicbox_ide_outbsync (ide_drive_t *drive, u8 value, unsigned long port) |
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{ |
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writew(value << 8, (void __iomem *) port); |
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} |
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static void magicbox_ide_outw (u16 value, unsigned long port) |
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{ |
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writew(value, (void __iomem *) port); |
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} |
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static void magicbox_ide_outsw (unsigned long port, void *addr, u32 count) |
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{ |
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u16 *ptr; |
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for (ptr = addr; count--; ptr++) |
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writew(*ptr, (void __iomem *) port); |
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} |
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static void magicbox_ide_outl (u32 value, unsigned long port) |
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{ |
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writel(value, (void __iomem *) port); |
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} |
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static void magicbox_ide_outsl (unsigned long port, void *addr, u32 count) |
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{ |
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u32 *ptr; |
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for (ptr = addr; count--; ptr++) |
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writel(*ptr, (void __iomem *) port); |
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} |
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static void __init ide_magicbox_register(unsigned long addr, |
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unsigned long caddr, int irq) |
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{ |
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hw_regs_t hw; |
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ide_hwif_t *hwif; |
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memset(&hw, 0, sizeof(hw)); |
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ide_setup_ports(&hw, addr, ide_offsets, caddr + 12, 0, NULL,irq); |
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if (ide_register_hw(&hw, &hwif) != -1) |
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{ |
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printk(KERN_NOTICE "magicbox-ide: Registered IDE-CF driver\n"); |
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hwif->mmio = 2; |
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hwif->drives[0].unmask = 1; |
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hwif->OUTB = magicbox_ide_outb; |
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hwif->OUTBSYNC = magicbox_ide_outbsync; |
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hwif->OUTW = magicbox_ide_outw; |
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hwif->OUTSW = magicbox_ide_outsw; |
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hwif->OUTSL = magicbox_ide_outsl; |
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hwif->INB = magicbox_ide_inb; |
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hwif->INW = magicbox_ide_inw; |
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hwif->INSW = magicbox_ide_insw; |
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hwif->INSL = magicbox_ide_insl; |
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} |
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} |
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void __init ide_magicbox_init(void) |
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{ |
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volatile u16 *addr; |
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volatile u16 *caddr; |
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/* Turn on PerWE instead of PCIsomething */ |
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mtdcr(DCRN_CPC0_PCI_BASE, mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27)); |
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/* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */ |
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mtdcr(DCRN_EBC_BASE, 1); |
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mtdcr(DCRN_EBC_BASE + 1, 0xff11a000); |
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mtdcr(DCRN_EBC_BASE, 0x11); |
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mtdcr(DCRN_EBC_BASE + 1, 0x080bd800); |
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|
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/* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */ |
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mtdcr(DCRN_EBC_BASE, 2); |
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mtdcr(DCRN_EBC_BASE + 1, 0xff21a000); |
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mtdcr(DCRN_EBC_BASE, 0x12); |
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mtdcr(DCRN_EBC_BASE + 1, 0x080bd800); |
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/* Remap physical address space */ |
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addr = ioremap_nocache(0xff100000, 4096); |
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caddr = ioremap_nocache(0xff200000, 4096); |
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|
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/* Set interrupt to low-to-high-edge-triggered */ |
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mtdcr(UIC0_TR, mfdcr(UIC0_TR) & ~(0x80000000L >> IRQ)); |
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mtdcr(UIC0_PR, mfdcr(UIC0_PR) | (0x80000000L >> IRQ)); |
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ide_magicbox_register((unsigned long)addr, (unsigned long)caddr, IRQ); |
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} |
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@ -0,0 +1,113 @@ |
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/*
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* magicmap.c: Copyleft 2005 Karol Lewandowski |
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* |
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* Mapping for MagicBox flash. |
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* Based on walnut.c. |
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* |
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* Heikki Lindholm <holindho@infradead.org> |
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* |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/map.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/autoconf.h> |
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#include <asm/io.h> |
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static struct mtd_info *flash; |
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static struct map_info magic_map = { |
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.name = "Magically mapped flash", |
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.phys = 0xffc00000, |
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.size = 0x400000, |
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.bankwidth = 2, |
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}; |
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|
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static struct mtd_partition magic_partitions[] = { |
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{ |
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.name = "linux", |
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.offset = 0x0, |
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.size = 0x3c0000, |
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}, |
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{ |
||||
.name = "rootfs", |
||||
.offset = 0x100000, |
||||
.size = 0x2c0000, |
||||
}, |
||||
{ |
||||
.name = "bootloader", |
||||
.offset = 0x3c0000, |
||||
.size = 0x040000, |
||||
.mask_flags = MTD_WRITEABLE, |
||||
}, |
||||
}; |
||||
|
||||
int __init init_magic(void) |
||||
{ |
||||
u32 size, len; |
||||
|
||||
magic_map.virt = |
||||
(void __iomem *)ioremap(magic_map.phys, magic_map.size); |
||||
|
||||
if (!magic_map.virt) { |
||||
printk("Failed to ioremap flash.\n"); |
||||
return -EIO; |
||||
} |
||||
|
||||
simple_map_init(&magic_map); |
||||
|
||||
flash = do_map_probe("cfi_probe", &magic_map); |
||||
if (flash) { |
||||
flash->owner = THIS_MODULE; |
||||
if (flash->read(flash, 12, sizeof(u32), &len, (char *) &size) || |
||||
len != 4) |
||||
return -ENXIO; |
||||
size += 0x40; /* header size of the uImage */ |
||||
if (size < 0x400000) { |
||||
/* skip to next erase block */ |
||||
if (size & (flash->erasesize - 1)) { |
||||
size |= (flash->erasesize - 1); |
||||
size += 1; |
||||
} |
||||
magic_partitions[1].offset = size; |
||||
magic_partitions[1].size = magic_partitions[2].offset - size; |
||||
} |
||||
|
||||
add_mtd_partitions(flash, magic_partitions, |
||||
ARRAY_SIZE(magic_partitions)); |
||||
} else { |
||||
printk("map probe failed for flash\n"); |
||||
return -ENXIO; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void __exit cleanup_magic(void) |
||||
{ |
||||
if (flash) { |
||||
del_mtd_partitions(flash); |
||||
map_destroy(flash); |
||||
} |
||||
|
||||
if (magic_map.virt) { |
||||
iounmap((void *)magic_map.virt); |
||||
magic_map.virt = NULL; |
||||
} |
||||
} |
||||
|
||||
module_init(init_magic); |
||||
module_exit(cleanup_magic); |
||||
|
||||
MODULE_LICENSE("GPL"); |
||||
MODULE_AUTHOR("Karol Lewandowski"); |
||||
MODULE_DESCRIPTION("MTD map and partitions for IBM 405EP MagicBox boards"); |
File diff suppressed because it is too large
Load Diff
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Reference in new issue