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@ -107,7 +107,7 @@ |
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#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7) |
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#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11) |
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#define IFXMIPS_RCU_RST_REQ_ARC_JTAG (1 << 20) |
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/*------------ MCD */ |
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@ -189,10 +189,10 @@ |
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#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600 |
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#define IFXMIPS_PPE32_MEM_MAP (IFXMIPS_PPE32_BASE_ADDR + 0x10000 ) |
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#define IFXMIPS_PPE32_MEM_MAP ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10000)) |
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#define IFXMIPS_PPE32_SRST ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10080)) |
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#define MII_MODE 1 |
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#define REV_MII_MODE 2 |
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/* mdio access */ |
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@ -420,4 +420,10 @@ |
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#define MEI_XMEM_BAR15 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0090)) |
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#define MEI_XMEM_BAR16 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0094)) |
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/*------------ FUSE */ |
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#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354) |
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#endif |
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