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390 lines
13 KiB
390 lines
13 KiB
![]()
6 years ago
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From fd1a1eabf2473e769b5cafc704e0336d11f61961 Mon Sep 17 00:00:00 2001
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From: RogerCC Lin <rogercc.lin@mediatek.com>
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Date: Thu, 30 Nov 2017 22:10:44 +0800
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Subject: [PATCH 166/224] mtd: nand: mtk: Support different MTK NAND flash
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controller IP
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MT7622 uses an MTK's earlier NAND flash controller IP which support
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different sector size, max spare size per sector and paraity bits...,
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some register's offset and definition also been changed in the NAND
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flash controller, this patch is the preparation to support MT7622
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NAND flash controller.
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MT7622 NFC and ECC engine are similar to MT2701's, except below
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differences:
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(1)MT7622 NFC's max sector size(ECC data size) is 512 bytes, and
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MT2701's is 1024, and MT7622's max sector number is 8.
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(2)The parity bit of MT7622 is 13, MT2701 is 14.
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(3)MT7622 ECC supports less ECC strength, max to 16 bit ecc strength.
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(4)MT7622 supports less spare size per sector, max spare size per
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sector is 28 bytes.
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(5)Some register's offset are different, include ECC_ENCIRQ_EN,
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ECC_ENCIRQ_STA, ECC_DECDONE, ECC_DECIRQ_EN and ECC_DECIRQ_STA.
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(6)ENC_MODE of ECC_ENCCNFG register is moved from bit 5-6 to bit 4-5.
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Signed-off-by: RogerCC Lin <rogercc.lin@mediatek.com>
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Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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---
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drivers/mtd/nand/mtk_ecc.c | 100 ++++++++++++++++++++++++++++++--------------
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drivers/mtd/nand/mtk_ecc.h | 3 +-
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drivers/mtd/nand/mtk_nand.c | 27 ++++++++----
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3 files changed, 89 insertions(+), 41 deletions(-)
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diff --git a/drivers/mtd/nand/mtk_ecc.c b/drivers/mtd/nand/mtk_ecc.c
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index c51d214d169e..6610eefaa92b 100644
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--- a/drivers/mtd/nand/mtk_ecc.c
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+++ b/drivers/mtd/nand/mtk_ecc.c
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@@ -34,34 +34,28 @@
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#define ECC_ENCCON (0x00)
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#define ECC_ENCCNFG (0x04)
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-#define ECC_MODE_SHIFT (5)
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#define ECC_MS_SHIFT (16)
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#define ECC_ENCDIADDR (0x08)
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#define ECC_ENCIDLE (0x0C)
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-#define ECC_ENCIRQ_EN (0x80)
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-#define ECC_ENCIRQ_STA (0x84)
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#define ECC_DECCON (0x100)
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#define ECC_DECCNFG (0x104)
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#define DEC_EMPTY_EN BIT(31)
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#define DEC_CNFG_CORRECT (0x3 << 12)
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#define ECC_DECIDLE (0x10C)
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#define ECC_DECENUM0 (0x114)
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-#define ECC_DECDONE (0x124)
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-#define ECC_DECIRQ_EN (0x200)
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-#define ECC_DECIRQ_STA (0x204)
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#define ECC_TIMEOUT (500000)
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#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
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#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
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-#define ECC_IRQ_REG(op) ((op) == ECC_ENCODE ? \
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- ECC_ENCIRQ_EN : ECC_DECIRQ_EN)
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struct mtk_ecc_caps {
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u32 err_mask;
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const u8 *ecc_strength;
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+ const u32 *ecc_regs;
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u8 num_ecc_strength;
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- u32 encode_parity_reg0;
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+ u8 ecc_mode_shift;
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+ u32 parity_bits;
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int pg_irq_sel;
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};
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@@ -89,6 +83,33 @@ static const u8 ecc_strength_mt2712[] = {
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40, 44, 48, 52, 56, 60, 68, 72, 80
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};
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+enum mtk_ecc_regs {
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+ ECC_ENCPAR00,
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+ ECC_ENCIRQ_EN,
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+ ECC_ENCIRQ_STA,
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+ ECC_DECDONE,
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+ ECC_DECIRQ_EN,
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+ ECC_DECIRQ_STA,
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+};
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+
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+static int mt2701_ecc_regs[] = {
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+ [ECC_ENCPAR00] = 0x10,
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+ [ECC_ENCIRQ_EN] = 0x80,
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+ [ECC_ENCIRQ_STA] = 0x84,
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+ [ECC_DECDONE] = 0x124,
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+ [ECC_DECIRQ_EN] = 0x200,
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+ [ECC_DECIRQ_STA] = 0x204,
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+};
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+
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+static int mt2712_ecc_regs[] = {
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+ [ECC_ENCPAR00] = 0x300,
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+ [ECC_ENCIRQ_EN] = 0x80,
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+ [ECC_ENCIRQ_STA] = 0x84,
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+ [ECC_DECDONE] = 0x124,
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+ [ECC_DECIRQ_EN] = 0x200,
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+ [ECC_DECIRQ_STA] = 0x204,
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+};
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+
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static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
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enum mtk_ecc_operation op)
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{
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@@ -107,32 +128,30 @@ static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
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static irqreturn_t mtk_ecc_irq(int irq, void *id)
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{
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struct mtk_ecc *ecc = id;
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- enum mtk_ecc_operation op;
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u32 dec, enc;
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- dec = readw(ecc->regs + ECC_DECIRQ_STA) & ECC_IRQ_EN;
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+ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
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+ & ECC_IRQ_EN;
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if (dec) {
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- op = ECC_DECODE;
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- dec = readw(ecc->regs + ECC_DECDONE);
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+ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
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if (dec & ecc->sectors) {
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/*
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* Clear decode IRQ status once again to ensure that
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* there will be no extra IRQ.
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*/
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- readw(ecc->regs + ECC_DECIRQ_STA);
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+ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
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ecc->sectors = 0;
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complete(&ecc->done);
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} else {
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return IRQ_HANDLED;
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}
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} else {
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- enc = readl(ecc->regs + ECC_ENCIRQ_STA) & ECC_IRQ_EN;
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- if (enc) {
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- op = ECC_ENCODE;
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+ enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
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+ & ECC_IRQ_EN;
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+ if (enc)
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complete(&ecc->done);
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- } else {
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+ else
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return IRQ_NONE;
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- }
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}
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return IRQ_HANDLED;
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@@ -160,7 +179,7 @@ static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
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/* configure ECC encoder (in bits) */
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enc_sz = config->len << 3;
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- reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
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+ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
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reg |= (enc_sz << ECC_MS_SHIFT);
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writel(reg, ecc->regs + ECC_ENCCNFG);
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@@ -171,9 +190,9 @@ static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
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} else {
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/* configure ECC decoder (in bits) */
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dec_sz = (config->len << 3) +
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- config->strength * ECC_PARITY_BITS;
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+ config->strength * ecc->caps->parity_bits;
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- reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
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+ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
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reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
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reg |= DEC_EMPTY_EN;
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writel(reg, ecc->regs + ECC_DECCNFG);
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@@ -291,7 +310,12 @@ int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
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*/
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if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
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reg_val |= ECC_PG_IRQ_SEL;
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- writew(reg_val, ecc->regs + ECC_IRQ_REG(op));
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+ if (op == ECC_ENCODE)
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+ writew(reg_val, ecc->regs +
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+ ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
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+ else
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+ writew(reg_val, ecc->regs +
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+ ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
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}
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writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
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@@ -310,13 +334,17 @@ void mtk_ecc_disable(struct mtk_ecc *ecc)
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/* disable it */
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mtk_ecc_wait_idle(ecc, op);
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- if (op == ECC_DECODE)
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+ if (op == ECC_DECODE) {
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/*
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* Clear decode IRQ status in case there is a timeout to wait
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* decode IRQ.
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*/
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- readw(ecc->regs + ECC_DECIRQ_STA);
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- writew(0, ecc->regs + ECC_IRQ_REG(op));
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+ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
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+ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
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+ } else {
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+ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
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+ }
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+
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writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
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mutex_unlock(&ecc->lock);
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@@ -367,11 +395,11 @@ int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
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mtk_ecc_wait_idle(ecc, ECC_ENCODE);
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/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
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- len = (config->strength * ECC_PARITY_BITS + 7) >> 3;
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+ len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
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/* write the parity bytes generated by the ECC back to temp buffer */
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__ioread32_copy(ecc->eccdata,
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- ecc->regs + ecc->caps->encode_parity_reg0,
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+ ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
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round_up(len, 4));
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/* copy into possibly unaligned OOB region with actual length */
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@@ -404,19 +432,29 @@ void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
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}
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EXPORT_SYMBOL(mtk_ecc_adjust_strength);
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+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
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+{
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+ return ecc->caps->parity_bits;
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+}
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+EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
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+
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static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
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.err_mask = 0x3f,
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.ecc_strength = ecc_strength_mt2701,
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+ .ecc_regs = mt2701_ecc_regs,
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.num_ecc_strength = 20,
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- .encode_parity_reg0 = 0x10,
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+ .ecc_mode_shift = 5,
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+ .parity_bits = 14,
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.pg_irq_sel = 0,
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};
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static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
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.err_mask = 0x7f,
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.ecc_strength = ecc_strength_mt2712,
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+ .ecc_regs = mt2712_ecc_regs,
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.num_ecc_strength = 23,
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- .encode_parity_reg0 = 0x300,
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+ .ecc_mode_shift = 5,
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+ .parity_bits = 14,
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.pg_irq_sel = 1,
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};
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@@ -452,7 +490,7 @@ static int mtk_ecc_probe(struct platform_device *pdev)
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max_eccdata_size = ecc->caps->num_ecc_strength - 1;
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max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
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- max_eccdata_size = (max_eccdata_size * ECC_PARITY_BITS + 7) >> 3;
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+ max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
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max_eccdata_size = round_up(max_eccdata_size, 4);
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ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
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if (!ecc->eccdata)
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diff --git a/drivers/mtd/nand/mtk_ecc.h b/drivers/mtd/nand/mtk_ecc.h
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index d245c14f1b80..a455df080952 100644
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--- a/drivers/mtd/nand/mtk_ecc.h
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+++ b/drivers/mtd/nand/mtk_ecc.h
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@@ -14,8 +14,6 @@
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#include <linux/types.h>
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-#define ECC_PARITY_BITS (14)
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-
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enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
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enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
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@@ -43,6 +41,7 @@ int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
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int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
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void mtk_ecc_disable(struct mtk_ecc *);
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void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
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+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
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struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
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void mtk_ecc_release(struct mtk_ecc *);
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diff --git a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c
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index 6d0101e13ef6..7349aa846f9a 100644
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--- a/drivers/mtd/nand/mtk_nand.c
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+++ b/drivers/mtd/nand/mtk_nand.c
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@@ -97,7 +97,6 @@
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#define MTK_TIMEOUT (500000)
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#define MTK_RESET_TIMEOUT (1000000)
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-#define MTK_MAX_SECTOR (16)
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#define MTK_NAND_MAX_NSELS (2)
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#define MTK_NFC_MIN_SPARE (16)
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#define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \
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@@ -109,6 +108,8 @@ struct mtk_nfc_caps {
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u8 num_spare_size;
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u8 pageformat_spare_shift;
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u8 nfi_clk_div;
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+ u8 max_sector;
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+ u32 max_sector_size;
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};
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struct mtk_nfc_bad_mark_ctl {
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@@ -450,7 +451,7 @@ static inline u8 mtk_nfc_read_byte(struct mtd_info *mtd)
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* set to max sector to allow the HW to continue reading over
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* unaligned accesses
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*/
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- reg = (MTK_MAX_SECTOR << CON_SEC_SHIFT) | CON_BRD;
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+ reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD;
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nfi_writel(nfc, reg, NFI_CON);
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/* trigger to fetch data */
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@@ -481,7 +482,7 @@ static void mtk_nfc_write_byte(struct mtd_info *mtd, u8 byte)
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reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
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nfi_writew(nfc, reg, NFI_CNFG);
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- reg = MTK_MAX_SECTOR << CON_SEC_SHIFT | CON_BWR;
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+ reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR;
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nfi_writel(nfc, reg, NFI_CON);
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nfi_writew(nfc, STAR_EN, NFI_STRDATA);
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@@ -1126,9 +1127,11 @@ static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
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{
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struct nand_chip *nand = mtd_to_nand(mtd);
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struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
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+ struct mtk_nfc *nfc = nand_get_controller_data(nand);
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u32 ecc_bytes;
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- ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * ECC_PARITY_BITS, 8);
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+ ecc_bytes = DIV_ROUND_UP(nand->ecc.strength *
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+ mtk_ecc_get_parity_bits(nfc->ecc), 8);
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fdm->reg_size = chip->spare_per_sector - ecc_bytes;
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if (fdm->reg_size > NFI_FDM_MAX_SIZE)
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@@ -1208,7 +1211,8 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
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* this controller only supports 512 and 1024 sizes
|
||
|
*/
|
||
|
if (nand->ecc.size < 1024) {
|
||
|
- if (mtd->writesize > 512) {
|
||
|
+ if (mtd->writesize > 512 &&
|
||
|
+ nfc->caps->max_sector_size > 512) {
|
||
|
nand->ecc.size = 1024;
|
||
|
nand->ecc.strength <<= 1;
|
||
|
} else {
|
||
|
@@ -1223,7 +1227,8 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
|
||
|
return ret;
|
||
|
|
||
|
/* calculate oob bytes except ecc parity data */
|
||
|
- free = ((nand->ecc.strength * ECC_PARITY_BITS) + 7) >> 3;
|
||
|
+ free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc)
|
||
|
+ + 7) >> 3;
|
||
|
free = spare - free;
|
||
|
|
||
|
/*
|
||
|
@@ -1233,10 +1238,12 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
|
||
|
*/
|
||
|
if (free > NFI_FDM_MAX_SIZE) {
|
||
|
spare -= NFI_FDM_MAX_SIZE;
|
||
|
- nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS;
|
||
|
+ nand->ecc.strength = (spare << 3) /
|
||
|
+ mtk_ecc_get_parity_bits(nfc->ecc);
|
||
|
} else if (free < 0) {
|
||
|
spare -= NFI_FDM_MIN_SIZE;
|
||
|
- nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS;
|
||
|
+ nand->ecc.strength = (spare << 3) /
|
||
|
+ mtk_ecc_get_parity_bits(nfc->ecc);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
@@ -1389,6 +1396,8 @@ static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
|
||
|
.num_spare_size = 16,
|
||
|
.pageformat_spare_shift = 4,
|
||
|
.nfi_clk_div = 1,
|
||
|
+ .max_sector = 16,
|
||
|
+ .max_sector_size = 1024,
|
||
|
};
|
||
|
|
||
|
static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
|
||
|
@@ -1396,6 +1405,8 @@ static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
|
||
|
.num_spare_size = 19,
|
||
|
.pageformat_spare_shift = 16,
|
||
|
.nfi_clk_div = 2,
|
||
|
+ .max_sector = 16,
|
||
|
+ .max_sector_size = 1024,
|
||
|
};
|
||
|
|
||
|
static const struct of_device_id mtk_nfc_id_table[] = {
|
||
|
--
|
||
|
2.11.0
|
||
|
|