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--- a/arch/mips/ath79/common.c
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+++ b/arch/mips/ath79/common.c
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@@ -38,7 +38,7 @@ unsigned int ath79_soc_rev;
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void __iomem *ath79_pll_base;
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void __iomem *ath79_reset_base;
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EXPORT_SYMBOL_GPL(ath79_reset_base);
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-static void __iomem *ath79_ddr_base;
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+void __iomem *ath79_ddr_base;
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static void __iomem *ath79_ddr_wb_flush_base;
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static void __iomem *ath79_ddr_pci_win_base;
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -32,7 +32,7 @@
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#define AR71XX_SPI_SIZE 0x01000000
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#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
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-#define AR71XX_DDR_CTRL_SIZE 0x100
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+#define AR71XX_DDR_CTRL_SIZE 0x200
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#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR71XX_UART_SIZE 0x100
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#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
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@@ -229,6 +229,9 @@
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#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
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#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
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+#define QCA955X_DDR_CTL_CONFIG 0x108
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+#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC BIT(23)
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+
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/*
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* PLL block
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*/
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -165,6 +165,27 @@ static void qca953x_wmac_setup(void)
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ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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}
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+static int ar955x_wmac_reset(void)
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+{
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+ int i;
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+
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+ /* Try to wait for WMAC DDR activity to stop */
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+ for (i = 0; i < 10; i++) {
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+ if (!(__raw_readl(ath79_ddr_base + QCA955X_DDR_CTL_CONFIG) &
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+ QCA955X_DDR_CTL_CONFIG_ACT_WMAC))
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+ break;
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+
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+ udelay(10);
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+ }
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+
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+ ath79_device_reset_set(QCA955X_RESET_RTC);
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+ udelay(10);
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+ ath79_device_reset_clear(QCA955X_RESET_RTC);
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+ udelay(10);
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+
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+ return 0;
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+}
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+
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static void qca955x_wmac_setup(void)
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{
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u32 t;
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@@ -181,6 +202,8 @@ static void qca955x_wmac_setup(void)
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ath79_wmac_data.is_clk_25mhz = false;
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else
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ath79_wmac_data.is_clk_25mhz = true;
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+
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+ ath79_wmac_data.external_reset = ar955x_wmac_reset;
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}
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#define AR93XX_WMAC_SIZE \
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--- a/arch/mips/ath79/common.h
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+++ b/arch/mips/ath79/common.h
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@@ -19,6 +19,8 @@
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#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
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#define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024)
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+extern void __iomem *ath79_ddr_base;
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+
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void ath79_clocks_init(void);
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unsigned long ath79_get_sys_clk_rate(const char *id);
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