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24 lines
757 B
24 lines
757 B
7 years ago
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From: Felix Fietkau <nbd@nbd.name>
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Date: Wed, 18 May 2016 18:03:31 +0200
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Subject: [PATCH] MIPS: ath79: fix register address in ath79_ddr_wb_flush()
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ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
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need to be a multiple of 4.
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Cc: Alban Bedel <albeu@free.fr>
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Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/mips/ath79/common.c
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+++ b/arch/mips/ath79/common.c
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@@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
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void ath79_ddr_wb_flush(u32 reg)
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{
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- void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
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+ void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg * 4;
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/* Flush the DDR write buffer. */
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__raw_writel(0x1, flush_reg);
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