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403 lines
12 KiB
403 lines
12 KiB
6 years ago
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From c2b82810c0272bb29a9b426b017b196436957c76 Mon Sep 17 00:00:00 2001
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From: Matthias Reichl <hias@horus.com>
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Date: Sun, 7 May 2017 11:34:26 +0200
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Subject: [PATCH 115/454] ASoC: bcm2835: Add support for TDM modes
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bcm2835 supports arbitrary positioning of channel data within
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a frame and thus is capable of supporting TDM modes. Since
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the driver is limited to 2-channel operations only TDM setups
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with exactly 2 active slots are supported.
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Logical TDM slot numbering follows the usual convention:
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For I2S-like modes, with a 50% duty-cycle frame clock,
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slots 0, 2, ... are transmitted in the first half of a frame,
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slots 1, 3, ... are transmitted in the second half.
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For DSP modes slot numbering is ascending: 0, 1, 2, 3, ...
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Channel position calculation has been refactored to use
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TDM info and moved out of hw_params.
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set_tdm_slot, set_bclk_ratio and hw_params now check more
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strictly if the configuration is valid. Illegal configurations
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like odd number of slots in I2S mode, data lengths exceeding
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slot width or frame sizes larger than the hardware limit of
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1024 are rejected. Also hw_params now properly checks for
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errors from clk_set_rate.
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Allowed PCM formats are already guarded by stream constraints,
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thus the formats check in hw_params has been removed and
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data_length is now retrieved via params_width().
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Also standard functions like snd_soc_params_to_bclk are now
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being used instead of manual calculations to make the code
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more readable.
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Special care has been taken to ensure that set_bclk_ratio works
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as before. The bclk ratio is mapped to a 2-channel TDM config
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with a slot width of half the ratio. In order to support odd ratios,
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which can't be expressed via a TDM config, the ratio (frame length)
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is stored and used by hw_params.
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Signed-off-by: Matthias Reichl <hias@horus.com>
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---
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sound/soc/bcm/bcm2835-i2s.c | 243 ++++++++++++++++++++++++++++--------
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1 file changed, 190 insertions(+), 53 deletions(-)
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--- a/sound/soc/bcm/bcm2835-i2s.c
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+++ b/sound/soc/bcm/bcm2835-i2s.c
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@@ -31,6 +31,7 @@
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* General Public License for more details.
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*/
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+#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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@@ -99,6 +100,8 @@
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#define BCM2835_I2S_CHWID(v) (v)
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#define BCM2835_I2S_CH1(v) ((v) << 16)
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#define BCM2835_I2S_CH2(v) (v)
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+#define BCM2835_I2S_CH1_POS(v) BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(v))
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+#define BCM2835_I2S_CH2_POS(v) BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(v))
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#define BCM2835_I2S_TX_PANIC(v) ((v) << 24)
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#define BCM2835_I2S_RX_PANIC(v) ((v) << 16)
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@@ -110,12 +113,19 @@
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#define BCM2835_I2S_INT_RXR BIT(1)
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#define BCM2835_I2S_INT_TXW BIT(0)
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+/* Frame length register is 10 bit, maximum length 1024 */
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+#define BCM2835_I2S_MAX_FRAME_LENGTH 1024
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+
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/* General device struct */
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struct bcm2835_i2s_dev {
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struct device *dev;
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struct snd_dmaengine_dai_dma_data dma_data[2];
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unsigned int fmt;
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- unsigned int bclk_ratio;
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+ unsigned int tdm_slots;
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+ unsigned int rx_mask;
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+ unsigned int tx_mask;
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+ unsigned int slot_width;
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+ unsigned int frame_length;
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struct regmap *i2s_regmap;
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struct clk *clk;
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@@ -225,19 +235,117 @@ static int bcm2835_i2s_set_dai_bclk_rati
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unsigned int ratio)
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{
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struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
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- dev->bclk_ratio = ratio;
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+
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+ if (!ratio) {
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+ dev->tdm_slots = 0;
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+ return 0;
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+ }
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+
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+ if (ratio > BCM2835_I2S_MAX_FRAME_LENGTH)
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+ return -EINVAL;
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+
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+ dev->tdm_slots = 2;
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+ dev->rx_mask = 0x03;
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+ dev->tx_mask = 0x03;
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+ dev->slot_width = ratio / 2;
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+ dev->frame_length = ratio;
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+
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return 0;
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}
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+static int bcm2835_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai,
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+ unsigned int tx_mask, unsigned int rx_mask,
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+ int slots, int width)
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+{
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+ struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
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+
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+ if (slots) {
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+ if (slots < 0 || width < 0)
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+ return -EINVAL;
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+
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+ /* Limit masks to available slots */
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+ rx_mask &= GENMASK(slots - 1, 0);
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+ tx_mask &= GENMASK(slots - 1, 0);
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+
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+ /*
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+ * The driver is limited to 2-channel setups.
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+ * Check that exactly 2 bits are set in the masks.
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+ */
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+ if (hweight_long((unsigned long) rx_mask) != 2
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+ || hweight_long((unsigned long) tx_mask) != 2)
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+ return -EINVAL;
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+
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+ if (slots * width > BCM2835_I2S_MAX_FRAME_LENGTH)
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+ return -EINVAL;
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+ }
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+
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+ dev->tdm_slots = slots;
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+
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+ dev->rx_mask = rx_mask;
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+ dev->tx_mask = tx_mask;
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+ dev->slot_width = width;
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+ dev->frame_length = slots * width;
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+
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+ return 0;
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+}
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+
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+/*
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+ * Convert logical slot number into physical slot number.
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+ *
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+ * If odd_offset is 0 sequential number is identical to logical number.
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+ * This is used for DSP modes with slot numbering 0 1 2 3 ...
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+ *
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+ * Otherwise odd_offset defines the physical offset for odd numbered
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+ * slots. This is used for I2S and left/right justified modes to
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+ * translate from logical slot numbers 0 1 2 3 ... into physical slot
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+ * numbers 0 2 ... 3 4 ...
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+ */
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+static int bcm2835_i2s_convert_slot(unsigned int slot, unsigned int odd_offset)
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+{
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+ if (!odd_offset)
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+ return slot;
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+
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+ if (slot & 1)
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+ return (slot >> 1) + odd_offset;
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+
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+ return slot >> 1;
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+}
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+
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+/*
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+ * Calculate channel position from mask and slot width.
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+ *
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+ * Mask must contain exactly 2 set bits.
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+ * Lowest set bit is channel 1 position, highest set bit channel 2.
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+ * The constant offset is added to both channel positions.
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+ *
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+ * If odd_offset is > 0 slot positions are translated to
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+ * I2S-style TDM slot numbering ( 0 2 ... 3 4 ...) with odd
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+ * logical slot numbers starting at physical slot odd_offset.
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+ */
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+static void bcm2835_i2s_calc_channel_pos(
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+ unsigned int *ch1_pos, unsigned int *ch2_pos,
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+ unsigned int mask, unsigned int width,
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+ unsigned int bit_offset, unsigned int odd_offset)
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+{
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+ *ch1_pos = bcm2835_i2s_convert_slot((ffs(mask) - 1), odd_offset)
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+ * width + bit_offset;
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+ *ch2_pos = bcm2835_i2s_convert_slot((fls(mask) - 1), odd_offset)
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+ * width + bit_offset;
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+}
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+
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static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
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- unsigned int sampling_rate = params_rate(params);
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- unsigned int data_length, data_delay, bclk_ratio;
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- unsigned int ch1pos, ch2pos, mode, format;
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+ unsigned int data_length, data_delay, framesync_length;
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+ unsigned int slots, slot_width, odd_slot_offset;
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+ int frame_length, bclk_rate;
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+ unsigned int rx_mask, tx_mask;
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+ unsigned int rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos;
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+ unsigned int mode, format;
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uint32_t csreg;
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+ int ret = 0;
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/*
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* If a stream is already enabled,
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@@ -248,39 +356,44 @@ static int bcm2835_i2s_hw_params(struct
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if (csreg & (BCM2835_I2S_TXON | BCM2835_I2S_RXON))
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return 0;
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- /*
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- * Adjust the data length according to the format.
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- * We prefill the half frame length with an integer
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- * divider of 2400 as explained at the clock settings.
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- * Maybe it is overwritten there, if the Integer mode
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- * does not apply.
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- */
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- switch (params_format(params)) {
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- case SNDRV_PCM_FORMAT_S16_LE:
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- data_length = 16;
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- break;
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- case SNDRV_PCM_FORMAT_S24_LE:
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- data_length = 24;
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- break;
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- case SNDRV_PCM_FORMAT_S32_LE:
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- data_length = 32;
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- break;
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- default:
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- return -EINVAL;
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+ data_length = params_width(params);
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+ data_delay = 0;
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+ odd_slot_offset = 0;
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+ mode = 0;
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+
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+ if (dev->tdm_slots) {
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+ slots = dev->tdm_slots;
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+ slot_width = dev->slot_width;
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+ frame_length = dev->frame_length;
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+ rx_mask = dev->rx_mask;
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+ tx_mask = dev->tx_mask;
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+ bclk_rate = dev->frame_length * params_rate(params);
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+ } else {
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+ slots = 2;
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+ slot_width = params_width(params);
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+ rx_mask = 0x03;
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+ tx_mask = 0x03;
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+
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+ frame_length = snd_soc_params_to_frame_size(params);
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+ if (frame_length < 0)
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+ return frame_length;
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+
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+ bclk_rate = snd_soc_params_to_bclk(params);
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+ if (bclk_rate < 0)
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+ return bclk_rate;
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}
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- /* If bclk_ratio already set, use that one. */
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- if (dev->bclk_ratio)
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- bclk_ratio = dev->bclk_ratio;
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- else
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- /* otherwise calculate a fitting block ratio */
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- bclk_ratio = 2 * data_length;
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+ /* Check if data fits into slots */
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+ if (data_length > slot_width)
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+ return -EINVAL;
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/* Clock should only be set up here if CPU is clock master */
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switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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case SND_SOC_DAIFMT_CBS_CFM:
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- clk_set_rate(dev->clk, sampling_rate * bclk_ratio);
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+ ret = clk_set_rate(dev->clk, bclk_rate);
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+ if (ret)
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+ return ret;
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break;
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default:
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break;
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@@ -294,9 +407,26 @@ static int bcm2835_i2s_hw_params(struct
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format |= BCM2835_I2S_CHWID((data_length-8)&0xf);
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+ /* CH2 format is the same as for CH1 */
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+ format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format);
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+
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switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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+ /* I2S mode needs an even number of slots */
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+ if (slots & 1)
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+ return -EINVAL;
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+
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+ /*
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+ * Use I2S-style logical slot numbering: even slots
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+ * are in first half of frame, odd slots in second half.
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+ */
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+ odd_slot_offset = slots >> 1;
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+
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+ /* MSB starts one cycle after frame start */
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data_delay = 1;
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+
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+ /* Setup frame sync signal for 50% duty cycle */
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+ framesync_length = frame_length / 2;
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break;
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default:
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/*
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@@ -307,19 +437,10 @@ static int bcm2835_i2s_hw_params(struct
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return -EINVAL;
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}
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- ch1pos = data_delay;
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- ch2pos = bclk_ratio / 2 + data_delay;
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-
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- switch (params_channels(params)) {
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- case 2:
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- case 8:
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- format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format);
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- format |= BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(ch1pos));
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- format |= BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(ch2pos));
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- break;
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- default:
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- return -EINVAL;
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- }
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+ bcm2835_i2s_calc_channel_pos(&rx_ch1_pos, &rx_ch2_pos,
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+ rx_mask, slot_width, data_delay, odd_slot_offset);
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+ bcm2835_i2s_calc_channel_pos(&tx_ch1_pos, &tx_ch2_pos,
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+ tx_mask, slot_width, data_delay, odd_slot_offset);
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/*
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* Set format for both streams.
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@@ -327,11 +448,16 @@ static int bcm2835_i2s_hw_params(struct
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* (and therefore word length) anyway,
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* so the format will be the same.
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*/
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- regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG, format);
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- regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG, format);
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+ regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG,
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+ format
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+ | BCM2835_I2S_CH1_POS(rx_ch1_pos)
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+ | BCM2835_I2S_CH2_POS(rx_ch2_pos));
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+ regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG,
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+ format
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+ | BCM2835_I2S_CH1_POS(tx_ch1_pos)
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+ | BCM2835_I2S_CH2_POS(tx_ch2_pos));
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/* Setup the I2S mode */
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- mode = 0;
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if (data_length <= 16) {
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/*
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@@ -343,8 +469,8 @@ static int bcm2835_i2s_hw_params(struct
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mode |= BCM2835_I2S_FTXP | BCM2835_I2S_FRXP;
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}
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- mode |= BCM2835_I2S_FLEN(bclk_ratio - 1);
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- mode |= BCM2835_I2S_FSLEN(bclk_ratio / 2);
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+ mode |= BCM2835_I2S_FLEN(frame_length - 1);
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+ mode |= BCM2835_I2S_FSLEN(framesync_length);
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/* Master or slave? */
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switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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@@ -424,7 +550,20 @@ static int bcm2835_i2s_hw_params(struct
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/* Clear FIFOs */
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bcm2835_i2s_clear_fifos(dev, true, true);
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- return 0;
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+ dev_dbg(dev->dev,
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+ "slots: %d width: %d rx mask: 0x%02x tx_mask: 0x%02x\n",
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+ slots, slot_width, rx_mask, tx_mask);
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+
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+ dev_dbg(dev->dev, "frame len: %d sync len: %d data len: %d\n",
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+ frame_length, framesync_length, data_length);
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+
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+ dev_dbg(dev->dev, "rx pos: %d,%d tx pos: %d,%d\n",
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+ rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos);
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+
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+ dev_dbg(dev->dev, "sampling rate: %d bclk rate: %d\n",
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||
|
+ params_rate(params), bclk_rate);
|
||
|
+
|
||
|
+ return ret;
|
||
|
}
|
||
|
|
||
|
static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream,
|
||
|
@@ -560,6 +699,7 @@ static const struct snd_soc_dai_ops bcm2
|
||
|
.hw_params = bcm2835_i2s_hw_params,
|
||
|
.set_fmt = bcm2835_i2s_set_dai_fmt,
|
||
|
.set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio,
|
||
|
+ .set_tdm_slot = bcm2835_i2s_set_dai_tdm_slot,
|
||
|
};
|
||
|
|
||
|
static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai)
|
||
|
@@ -700,9 +840,6 @@ static int bcm2835_i2s_probe(struct plat
|
||
|
dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].flags =
|
||
|
SND_DMAENGINE_PCM_DAI_FLAG_PACK;
|
||
|
|
||
|
- /* BCLK ratio - use default */
|
||
|
- dev->bclk_ratio = 0;
|
||
|
-
|
||
|
/* Store the pdev */
|
||
|
dev->dev = &pdev->dev;
|
||
|
dev_set_drvdata(&pdev->dev, dev);
|