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From 90ebc4838666d148eac5bbac6f4044e5b25cd2d6 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
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Date: Sun, 18 Oct 2015 21:34:46 +0200
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Subject: [PATCH] serial: imx: repair and complete handshaking
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The .get_mctrl callback should not report the status of RTS or LOOP, so
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drop this. Instead implement reporting the state of CAR (aka DCD) and
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RI.
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For .set_mctrl implement setting the DTR line.
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Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Signed-off-by: Petr Štetiar <ynezz@true.cz>
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---
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drivers/tty/serial/imx.c | 23 +++++++++++++++++------
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1 file changed, 17 insertions(+), 6 deletions(-)
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--- a/drivers/tty/serial/imx.c
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+++ b/drivers/tty/serial/imx.c
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@@ -148,8 +148,11 @@
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#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
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#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
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#define USR2_IDLE (1<<12) /* Idle condition */
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+#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
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+#define USR2_RIIN (1<<9) /* Ring Indicator Input */
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#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
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#define USR2_WAKE (1<<7) /* Wake */
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+#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
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#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
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#define USR2_TXDC (1<<3) /* Transmitter complete */
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#define USR2_BRCD (1<<2) /* Break condition */
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@@ -804,16 +807,19 @@ static unsigned int imx_tx_empty(struct
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static unsigned int imx_get_mctrl(struct uart_port *port)
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{
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struct imx_port *sport = (struct imx_port *)port;
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- unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
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+ unsigned int tmp = TIOCM_DSR;
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+ unsigned usr1 = readl(sport->port.membase + USR1);
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- if (readl(sport->port.membase + USR1) & USR1_RTSS)
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+ if (usr1 & USR1_RTSS)
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tmp |= TIOCM_CTS;
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- if (readl(sport->port.membase + UCR2) & UCR2_CTS)
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- tmp |= TIOCM_RTS;
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-
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- if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
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- tmp |= TIOCM_LOOP;
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+ /* in DCE mode DCDIN is always 0 */
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+ if (!(usr1 & USR2_DCDIN))
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+ tmp |= TIOCM_CAR;
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+
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+ /* in DCE mode RIIN is always 0 */
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+ if (readl(sport->port.membase + USR2) & USR2_RIIN)
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+ tmp |= TIOCM_RI;
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return tmp;
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}
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@@ -831,6 +837,11 @@ static void imx_set_mctrl(struct uart_po
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writel(temp, sport->port.membase + UCR2);
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}
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+ temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
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+ if (!(mctrl & TIOCM_DTR))
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+ temp |= UCR3_DSR;
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+ writel(temp, sport->port.membase + UCR3);
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+
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temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
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if (mctrl & TIOCM_LOOP)
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temp |= UTS_LOOP;
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