|
|
|
|
From ff0b5fdb65bc7f10af7e83bb0919cb6bec2dc624 Mon Sep 17 00:00:00 2001
|
|
|
|
|
From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
|
|
|
|
|
Date: Mon, 23 Dec 2013 00:32:35 -0300
|
|
|
|
|
Subject: [PATCH] ARM: sunxi: add PLL4 support
|
|
|
|
|
MIME-Version: 1.0
|
|
|
|
|
Content-Type: text/plain; charset=UTF-8
|
|
|
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
|
|
|
|
|
|
This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
|
|
|
|
|
device trees. PLL4 is compatible with PLL1.
|
|
|
|
|
|
|
|
|
|
Signed-off-by: Emilio López <emilio@elopez.com.ar>
|
|
|
|
|
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
|
|
|
---
|
|
|
|
|
arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++++++
|
|
|
|
|
arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
|
|
|
|
|
arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++
|
|
|
|
|
arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
|
|
|
|
|
4 files changed, 28 insertions(+)
|
|
|
|
|
|
|
|
|
|
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
|
|
|
|
|
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
|
|
|
|
|
@@ -66,6 +66,13 @@
|
|
|
|
|
clocks = <&osc24M>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
+ pll4: pll4@01c20018 {
|
|
|
|
|
+ #clock-cells = <0>;
|
|
|
|
|
+ compatible = "allwinner,sun4i-pll1-clk";
|
|
|
|
|
+ reg = <0x01c20018 0x4>;
|
|
|
|
|
+ clocks = <&osc24M>;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
/* dummy is 200M */
|
|
|
|
|
cpu: cpu@01c20054 {
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
|
|
|
|
|
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
|
|
|
|
|
@@ -63,6 +63,13 @@
|
|
|
|
|
clocks = <&osc24M>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
+ pll4: pll4@01c20018 {
|
|
|
|
|
+ #clock-cells = <0>;
|
|
|
|
|
+ compatible = "allwinner,sun4i-pll1-clk";
|
|
|
|
|
+ reg = <0x01c20018 0x4>;
|
|
|
|
|
+ clocks = <&osc24M>;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
/* dummy is 200M */
|
|
|
|
|
cpu: cpu@01c20054 {
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
|
|
|
|
|
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
|
|
|
|
|
@@ -67,6 +67,13 @@
|
|
|
|
|
clocks = <&osc24M>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
+ pll4: pll4@01c20018 {
|
|
|
|
|
+ #clock-cells = <0>;
|
|
|
|
|
+ compatible = "allwinner,sun4i-pll1-clk";
|
|
|
|
|
+ reg = <0x01c20018 0x4>;
|
|
|
|
|
+ clocks = <&osc24M>;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
/* dummy is 200M */
|
|
|
|
|
cpu: cpu@01c20054 {
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
|
|
|
|
|
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
|
|
|
|
|
@@ -62,6 +62,13 @@
|
|
|
|
|
clocks = <&osc24M>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
+ pll4: pll4@01c20018 {
|
|
|
|
|
+ #clock-cells = <0>;
|
|
|
|
|
+ compatible = "allwinner,sun4i-pll1-clk";
|
|
|
|
|
+ reg = <0x01c20018 0x4>;
|
|
|
|
|
+ clocks = <&osc24M>;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
/*
|
|
|
|
|
* This is a dummy clock, to be used as placeholder on
|
|
|
|
|
* other mux clocks when a specific parent clock is not
|
