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From e8f13d2824871027e8b6d374a2db3672db043915 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 19 Mar 2012 15:53:37 +0100
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Subject: [PATCH 60/70] MIPS: lantiq: fixes danube clock
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---
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arch/mips/lantiq/xway/clk.c | 20 ++++++++++----------
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1 files changed, 10 insertions(+), 10 deletions(-)
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--- a/arch/mips/lantiq/xway/clk.c
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+++ b/arch/mips/lantiq/xway/clk.c
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@@ -181,7 +181,7 @@ unsigned long ltq_danube_io_region_clock
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{
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unsigned int ret = ltq_get_pll0_fosc();
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- switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
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+ switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0x3) {
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default:
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case 0:
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return (ret + 1) / 2;
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@@ -203,6 +203,15 @@ unsigned long ltq_danube_fpi_bus_clock(i
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return ret;
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}
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+unsigned long ltq_danube_fpi_hz(void)
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+{
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+ unsigned long ddr_clock = DDR_HZ;
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+
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+ if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
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+ return ddr_clock >> 1;
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+ return ddr_clock;
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+}
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+
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unsigned long ltq_danube_cpu_hz(void)
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{
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switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
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@@ -241,15 +250,6 @@ unsigned long ltq_ar9_cpu_hz(void)
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return ltq_ar9_sys_hz();
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}
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-unsigned long ltq_danube_fpi_hz(void)
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-{
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- unsigned long ddr_clock = DDR_HZ;
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-
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- if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
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- return ddr_clock >> 1;
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- return ddr_clock;
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-}
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-
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unsigned long ltq_vr9_cpu_hz(void)
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{
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unsigned int cpu_sel;
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