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60 lines
2.0 KiB
60 lines
2.0 KiB
9 years ago
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From 63243a4da7d0dfa19dcacd0a529782eeb2f86f92 Mon Sep 17 00:00:00 2001
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From: Simran Rai <ssimran@broadcom.com>
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Date: Mon, 19 Oct 2015 15:27:19 -0700
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Subject: [PATCH] clk: iproc: Fix PLL output frequency calculation
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This patch affects the clocks that use fractional ndivider in their
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PLL output frequency calculation. Instead of 2^20 divide factor, the
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clock's ndiv integer shift was used. Fixed the bug by replacing ndiv
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integer shift with 2^20 factor.
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Signed-off-by: Simran Rai <ssimran@broadcom.com>
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Signed-off-by: Ray Jui <rjui@broadcom.com>
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Reviewed-by: Scott Branden <sbranden@broadcom.com>
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Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
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Cc: <stable@vger.kernel.org> # v4.1+
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Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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---
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drivers/clk/bcm/clk-iproc-pll.c | 13 +++++--------
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1 file changed, 5 insertions(+), 8 deletions(-)
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--- a/drivers/clk/bcm/clk-iproc-pll.c
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+++ b/drivers/clk/bcm/clk-iproc-pll.c
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@@ -345,8 +345,8 @@ static unsigned long iproc_pll_recalc_ra
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struct iproc_pll *pll = clk->pll;
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const struct iproc_pll_ctrl *ctrl = pll->ctrl;
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u32 val;
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- u64 ndiv;
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- unsigned int ndiv_int, ndiv_frac, pdiv;
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+ u64 ndiv, ndiv_int, ndiv_frac;
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+ unsigned int pdiv;
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if (parent_rate == 0)
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return 0;
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@@ -366,22 +366,19 @@ static unsigned long iproc_pll_recalc_ra
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val = readl(pll->pll_base + ctrl->ndiv_int.offset);
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ndiv_int = (val >> ctrl->ndiv_int.shift) &
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bit_mask(ctrl->ndiv_int.width);
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- ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift;
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+ ndiv = ndiv_int << 20;
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if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
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val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
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ndiv_frac = (val >> ctrl->ndiv_frac.shift) &
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bit_mask(ctrl->ndiv_frac.width);
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-
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- if (ndiv_frac != 0)
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- ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) |
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- ndiv_frac;
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+ ndiv += ndiv_frac;
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}
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val = readl(pll->pll_base + ctrl->pdiv.offset);
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pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);
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- clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift;
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+ clk->rate = (ndiv * parent_rate) >> 20;
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if (pdiv == 0)
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clk->rate *= 2;
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