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From: Florian Fainelli <f.fainelli@gmail.com>
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Subject: [PATCH] ARM: BCM5301x: Disable MMU and Dcache during decompression
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Date: Tue, 14 Jul 2015 16:12:08 -0700
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Use the existing __armv7_mmu_cache_flush() to perform the cache flush
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since this does what we are after.
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/compressed/Makefile | 4 +++
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arch/arm/boot/compressed/head-bcm_5301x-mpcore.S | 37 ++++++++++++++++++++++++
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arch/arm/boot/compressed/head.S | 2 ++
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3 files changed, 43 insertions(+)
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create mode 100644 arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
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--- a/arch/arm/boot/compressed/Makefile
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+++ b/arch/arm/boot/compressed/Makefile
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@@ -31,6 +31,10 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
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OBJS += ll_char_wr.o font.o
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endif
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+ifeq ($(CONFIG_ARCH_BCM_5301X),y)
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+OBJS += head-bcm_5301x-mpcore.o
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+endif
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+
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ifeq ($(CONFIG_ARCH_SA1100),y)
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OBJS += head-sa1100.o
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endif
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--- /dev/null
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+++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
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@@ -0,0 +1,37 @@
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+/*
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+ *
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+ * Platform specific tweaks. This is merged into head.S by the linker.
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+ *
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+ */
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+
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+#include <linux/linkage.h>
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+#include <asm/assembler.h>
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+#include <asm/cp15.h>
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+
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+ .section ".start", "ax"
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+
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+/*
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+ * This code section is spliced into the head code by the linker
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+ */
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+
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+__plat_uncompress_start:
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+
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+ @ Preserve r8/r7 i.e. kernel entry values
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+ mov r12, r8
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+
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+ @ Clear MMU enable and Dcache enable bits
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+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
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+ bic r0, #CR_C|CR_M
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+ mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR
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+ nop
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+
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+ @ Call the cache invalidation routine
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+ bl __armv7_mmu_cache_flush_fn
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+ nop
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+ mov r0,#0
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+ ldr r3, =0x19022000 @ L2 cache controller, control reg
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+ str r0, [r3, #0x100] @ Disable L2 cache
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+ nop
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+
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+ @ Restore
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+ mov r8, r12
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--- a/arch/arm/boot/compressed/head.S
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+++ b/arch/arm/boot/compressed/head.S
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@@ -1152,6 +1152,7 @@ __armv7_mmu_cache_flush:
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hierarchical:
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mcr p15, 0, r10, c7, c10, 5 @ DMB
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stmfd sp!, {r0-r7, r9-r11}
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+ENTRY(__armv7_mmu_cache_flush_fn)
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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@@ -1201,6 +1202,7 @@ iflush:
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mcr p15, 0, r10, c7, c10, 4 @ DSB
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mcr p15, 0, r10, c7, c5, 4 @ ISB
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mov pc, lr
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+ENDPROC(__armv7_mmu_cache_flush_fn)
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__armv5tej_mmu_cache_flush:
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tst r4, #1
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