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49 lines
1.7 KiB
49 lines
1.7 KiB
11 years ago
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From fcfa66de8a2f0631a65a2cec0f6149dafd36ec81 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Mon, 5 Aug 2013 11:50:25 +0100
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Subject: [PATCH] MIPS: BMIPS: fix hardware interrupt routing for boot CPU != 0
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The hardware interrupt routing for boot CPU != 0 is wrong because it
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will route all the hardware interrupts to TP0 which is not the one we
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booted from. Fix this by properly checking which boot CPU we are booting
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from and updating the right interrupt mask for the boot CPU. This fixes
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booting on BCM3368 with bmips_smp_emabled = 0.
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Cc: blogic@openwrt.org
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Cc: jogo@openwrt.org
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Cc: cernekee@gmail.com
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Patchwork: https://patchwork.linux-mips.org/patch/5650/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/kernel/smp-bmips.c | 10 ++++++++--
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1 file changed, 8 insertions(+), 2 deletions(-)
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--- a/arch/mips/kernel/smp-bmips.c
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+++ b/arch/mips/kernel/smp-bmips.c
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@@ -66,6 +66,8 @@ static void __init bmips_smp_setup(void)
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int i, cpu = 1, boot_cpu = 0;
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#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
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+ int cpu_hw_intr;
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+
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/* arbitration priority */
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clear_c0_brcm_cmt_ctrl(0x30);
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@@ -80,8 +82,12 @@ static void __init bmips_smp_setup(void)
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* MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
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* MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
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*/
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- change_c0_brcm_cmt_intr(0xf8018000,
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- (0x02 << 27) | (0x03 << 15));
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+ if (boot_cpu == 0)
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+ cpu_hw_intr = 0x02;
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+ else
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+ cpu_hw_intr = 0x1d;
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+
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+ change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15));
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/* single core, 2 threads (2 pipelines) */
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max_cpus = 2;
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