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135 lines
4.0 KiB
135 lines
4.0 KiB
7 years ago
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From f98121f3ef3d36f4d040b11ab38f15387f6eefa2 Mon Sep 17 00:00:00 2001
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From: Arnd Bergmann <arnd@arndb.de>
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Date: Wed, 30 Nov 2016 15:08:55 +0100
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Subject: arm64: dts: fix build errors from missing dependencies
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Two branches were incorrectly sent without having the necessary
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header file changes. Rather than back those out now, I'm replacing
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the symbolic names for the clks and resets with the numeric
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values to get 'make allmodconfig dtbs' back to work.
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After the header file changes are merged, we can revert this
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patch.
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Fixes: 6bc37fa ("arm64: dts: add Allwinner A64 SoC .dtsi")
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Fixes: 50784e6 ("dts: arm64: db820c: add pmic pins specific dts file")
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Acked-by: Andre Przywara <andre.przywara@arm.com>
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Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 36 ++++++++++------------
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.../boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi | 2 +-
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2 files changed, 18 insertions(+), 20 deletions(-)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -42,10 +42,8 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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-#include <dt-bindings/clock/sun50i-a64-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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-#include <dt-bindings/reset/sun50i-a64-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -137,7 +135,7 @@
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&ccu CLK_BUS_PIO>;
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+ clocks = <&ccu 58>;
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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@@ -160,8 +158,8 @@
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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- clocks = <&ccu CLK_BUS_UART0>;
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- resets = <&ccu RST_BUS_UART0>;
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+ clocks = <&ccu 67>;
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+ resets = <&ccu 46>;
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status = "disabled";
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};
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@@ -171,8 +169,8 @@
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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- clocks = <&ccu CLK_BUS_UART1>;
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- resets = <&ccu RST_BUS_UART1>;
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+ clocks = <&ccu 68>;
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+ resets = <&ccu 47>;
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status = "disabled";
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};
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@@ -182,8 +180,8 @@
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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- clocks = <&ccu CLK_BUS_UART2>;
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- resets = <&ccu RST_BUS_UART2>;
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+ clocks = <&ccu 69>;
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+ resets = <&ccu 48>;
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status = "disabled";
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};
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@@ -193,8 +191,8 @@
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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- clocks = <&ccu CLK_BUS_UART3>;
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- resets = <&ccu RST_BUS_UART3>;
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+ clocks = <&ccu 70>;
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+ resets = <&ccu 49>;
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status = "disabled";
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};
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@@ -204,8 +202,8 @@
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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- clocks = <&ccu CLK_BUS_UART4>;
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- resets = <&ccu RST_BUS_UART4>;
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+ clocks = <&ccu 71>;
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+ resets = <&ccu 50>;
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status = "disabled";
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};
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@@ -213,8 +211,8 @@
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2ac00 0x400>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&ccu CLK_BUS_I2C0>;
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- resets = <&ccu RST_BUS_I2C0>;
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+ clocks = <&ccu 63>;
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+ resets = <&ccu 42>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -224,8 +222,8 @@
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b000 0x400>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&ccu CLK_BUS_I2C1>;
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- resets = <&ccu RST_BUS_I2C1>;
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+ clocks = <&ccu 64>;
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+ resets = <&ccu 43>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -235,8 +233,8 @@
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b400 0x400>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&ccu CLK_BUS_I2C2>;
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- resets = <&ccu RST_BUS_I2C2>;
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+ clocks = <&ccu 65>;
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+ resets = <&ccu 44>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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