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58 lines
1.8 KiB
58 lines
1.8 KiB
10 years ago
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From dd280a4cf6b826144f74d3fc4285633f1c337a1d Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Thu, 12 Jun 2014 11:28:47 -0500
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Subject: [PATCH 143/182] ata: qcom: Add device tree bindings information
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Add device tree binding for Qualcomm AHCI SATA controller and specifically
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the sata controller on the IPQ806x family of SoCs.
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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.../devicetree/bindings/ata/qcom-sata.txt | 40 ++++++++++++++++++++
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1 file changed, 40 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/ata/qcom-sata.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/ata/qcom-sata.txt
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@@ -0,0 +1,40 @@
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+* Qualcomm AHCI SATA Controller
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+
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+SATA nodes are defined to describe on-chip Serial ATA controllers.
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+Each SATA controller should have its own node.
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+
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+Required properties:
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+- compatible : compatible list, contains "qcom,msm-ahci"
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+- interrupts : <interrupt mapping for SATA IRQ>
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+- reg : <registers mapping>
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+- phys : Must contain exactly one entry as specified
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+ in phy-bindings.txt
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+- phy-names : Must be "sata-phy"
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+
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+Required properties for "qcom,ipq806x-ahci" compatible:
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+- clocks : Must contain an entry for each entry in clock-names.
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+- clock-names : Shall be:
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+ "slave_iface" - Fabric port AHB clock for SATA
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+ "iface" - AHB clock
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+ "core" - core clock
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+ "rxoob" - RX out-of-band clock
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+ "pmalive" - Power Module Alive clock
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+
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+Example:
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+ sata@29000000 {
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+ compatible = "qcom,ipq806x-ahci", "qcom,msm-ahci";
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+ reg = <0x29000000 0x180>;
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+
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+ interrupts = <0 209 0x0>;
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+
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+ clocks = <&gcc SFAB_SATA_S_H_CLK>,
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+ <&gcc SATA_H_CLK>,
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+ <&gcc SATA_A_CLK>,
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+ <&gcc SATA_RXOOB_CLK>,
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+ <&gcc SATA_PMALIVE_CLK>;
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+ clock-names = "slave_iface", "iface", "core",
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+ "rxoob", "pmalive";
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+
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+ phys = <&sata_phy>;
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+ phy-names = "sata-phy";
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+ };
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