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39 lines
1.3 KiB
39 lines
1.3 KiB
7 years ago
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -157,6 +157,10 @@
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#define QCA956X_EHCI0_BASE 0x1b000000
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#define QCA956X_EHCI1_BASE 0x1b400000
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#define QCA956X_EHCI_SIZE 0x200
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+#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
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+#define QCA956X_GMAC_SGMII_SIZE 0x64
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+#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
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+#define QCA956X_PLL_SIZE 0x50
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#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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#define QCA956X_GMAC_SIZE 0x64
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@@ -414,6 +418,7 @@
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#define QCA956X_PLL_DDR_CONFIG_REG 0x08
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#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
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#define QCA956X_PLL_CLK_CTRL_REG 0x10
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+#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
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#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
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#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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@@ -1196,4 +1201,16 @@
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#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
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#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
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+/*
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+ * QCA956X GMAC Interface
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+ */
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+
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+#define QCA956X_GMAC_REG_ETH_CFG 0x00
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+
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+#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
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+#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
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+#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
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+#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
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+#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
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+
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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