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80 lines
2.4 KiB
80 lines
2.4 KiB
10 years ago
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From e410b0069ee7c318a5b556f39b8b16814330a208 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 24 Jan 2014 17:01:17 +0100
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Subject: [PATCH 15/57] MIPS: ralink: cleanup early_printk
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Add support for the new MT7621/8 SoC and kill ifdefs.
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Cleanup some whitespace error while we are at it.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/early_printk.c | 45 ++++++++++++++++++++++++++-------------
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1 file changed, 30 insertions(+), 15 deletions(-)
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--- a/arch/mips/ralink/early_printk.c
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+++ b/arch/mips/ralink/early_printk.c
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@@ -12,21 +12,24 @@
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#include <asm/addrspace.h>
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#ifdef CONFIG_SOC_RT288X
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-#define EARLY_UART_BASE 0x300c00
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+#define EARLY_UART_BASE 0x300c00
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+#define CHIPID_BASE 0x300004
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+#elif defined(CONFIG_SOC_MT7621)
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+#define EARLY_UART_BASE 0x1E000c00
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+#define CHIPID_BASE 0x1E000004
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#else
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-#define EARLY_UART_BASE 0x10000c00
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+#define EARLY_UART_BASE 0x10000c00
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+#define CHIPID_BASE 0x10000004
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#endif
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-#define UART_REG_RX 0x00
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-#define UART_REG_TX 0x04
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-#define UART_REG_IER 0x08
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-#define UART_REG_IIR 0x0c
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-#define UART_REG_FCR 0x10
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-#define UART_REG_LCR 0x14
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-#define UART_REG_MCR 0x18
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-#define UART_REG_LSR 0x1c
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+#define MT7628_CHIP_NAME1 0x20203832
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+
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+#define UART_REG_TX 0x04
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+#define UART_REG_LSR 0x14
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+#define UART_REG_LSR_RT2880 0x1c
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static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
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+static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
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static inline void uart_w32(u32 val, unsigned reg)
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{
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@@ -38,11 +41,23 @@ static inline u32 uart_r32(unsigned reg)
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return __raw_readl(uart_membase + reg);
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}
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+static inline int soc_is_mt7628(void)
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+{
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+ return IS_ENABLED(CONFIG_SOC_MT7620) &&
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+ (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
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+}
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+
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void prom_putchar(unsigned char ch)
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{
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- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
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- ;
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- uart_w32(ch, UART_REG_TX);
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- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
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- ;
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+ if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
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+ uart_w32(ch, UART_TX);
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+ while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
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+ ;
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+ } else {
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+ while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
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+ ;
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+ uart_w32(ch, UART_REG_TX);
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+ while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
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+ ;
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+ }
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}
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