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From 3fe7841bf5a582dc7fd198e5bf70162ea418a22a Mon Sep 17 00:00:00 2001
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From: Koen Vandeputte <koen.vandeputte@ncentric.com>
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Date: Wed, 11 Sep 2019 11:02:19 +0200
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Subject: [PATCH] MIPS: ath79: Fix potentially missed IRQ handling during
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dispatch
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If both interrupts are set in the current implementation
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only the 1st will be handled and the 2nd will be skipped
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due to the "if else" condition.
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Fix this by using the same approach as done for QCA955x
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just below it.
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Fixes: fce5cc6e0ddc ("MIPS: ath79: add IRQ handling code for AR934X")
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Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
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CC: Felix Fietkau <nbd@nbd.name>
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CC: Gabor Juhos <juhosg@freemail.hu>
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CC: James Hogan <jhogan@kernel.org>
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CC: Paul Burton <paul.burton@mips.com>
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CC: Ralf Baechle <ralf@linux-mips.org>
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CC: stable@vger.kernel.org # v3.2+
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---
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arch/mips/ath79/irq.c | 12 +++++++++---
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1 file changed, 9 insertions(+), 3 deletions(-)
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--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -32,15 +32,21 @@ static void ar934x_ip2_irq_dispatch(stru
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u32 status;
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status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
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+ status &= AR934X_PCIE_WMAC_INT_PCIE_ALL | AR934X_PCIE_WMAC_INT_WMAC_ALL;
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+
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+ if (status == 0) {
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+ spurious_interrupt();
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+ return;
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+ }
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if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
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ath79_ddr_wb_flush(3);
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generic_handle_irq(ATH79_IP2_IRQ(0));
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- } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
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+ }
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+
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+ if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
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ath79_ddr_wb_flush(4);
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generic_handle_irq(ATH79_IP2_IRQ(1));
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- } else {
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- spurious_interrupt();
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}
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}
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