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From f7121d2b19ddad33a09408a2c5923bfd95da8533 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 6 Jan 2016 20:06:49 +0100
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Subject: [PATCH 017/102] clk: add hifsys reset
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Hi,
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small patch to add hifsys reset bits. Maybe you could add it to the next
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version of your patch series. i have teste scpsys and clk on mt7623 today
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and it works well.
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thanks,
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John
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/clk/mediatek/clk-mt2701.c | 2 ++
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include/dt-bindings/reset-controller/mt2701-resets.h | 9 +++++++++
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2 files changed, 11 insertions(+)
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--- a/drivers/clk/mediatek/clk-mt2701.c
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+++ b/drivers/clk/mediatek/clk-mt2701.c
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@@ -1000,6 +1000,8 @@ static void __init mtk_hifsys_init(struc
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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+
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+ mtk_register_reset_controller(node, 1, 0x34);
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}
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CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt2701-hifsys", mtk_hifsys_init);
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--- a/include/dt-bindings/reset-controller/mt2701-resets.h
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+++ b/include/dt-bindings/reset-controller/mt2701-resets.h
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@@ -71,4 +71,13 @@
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#define MT2701_TOPRGU_CONN_MCU_RST 12
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#define MT2701_TOPRGU_BDP_DISP_RST 13
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+/* HIFSYS resets */
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+#define MT2701_HIFSYS_UHOST0_RST 3
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+#define MT2701_HIFSYS_UHOST1_RST 4
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+#define MT2701_HIFSYS_UPHY0_RST 21
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+#define MT2701_HIFSYS_UPHY1_RST 22
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+#define MT2701_HIFSYS_PCIE0_RST 24
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+#define MT2701_HIFSYS_PCIE1_RST 25
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+#define MT2701_HIFSYS_PCIE2_RST 26
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+
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
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