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78 lines
2.1 KiB
78 lines
2.1 KiB
10 years ago
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From 7f94ebf35b017f1664e957857a7f36752e2577cd Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Wed, 5 Feb 2014 14:05:04 +0100
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Subject: [PATCH] ARM: sun6i: dt: Add PLL6 and SPI module clocks
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The module clocks in the A31 are still compatible with the A10 one. Add the SPI
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module clocks and the PLL6 in the device tree to allow their use by the SPI
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controllers.
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun6i-a31.dtsi | 46 ++++++++++++++++++++++++++++++++--------
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1 file changed, 37 insertions(+), 9 deletions(-)
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--- a/arch/arm/boot/dts/sun6i-a31.dtsi
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+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
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@@ -83,16 +83,12 @@
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clocks = <&osc24M>;
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};
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- /*
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- * This is a dummy clock, to be used as placeholder on
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- * other mux clocks when a specific parent clock is not
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- * yet implemented. It should be dropped when the driver
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- * is complete.
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- */
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- pll6: pll6 {
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+ pll6: clk@01c20028 {
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#clock-cells = <0>;
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- compatible = "fixed-clock";
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- clock-frequency = <0>;
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+ compatible = "allwinner,sun6i-a31-pll6-clk";
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+ reg = <0x01c20028 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll6";
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};
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cpu: cpu@01c20050 {
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@@ -192,6 +188,38 @@
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"apb2_uart1", "apb2_uart2", "apb2_uart3",
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"apb2_uart4", "apb2_uart5";
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};
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+
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+ spi0_clk: clk@01c200a0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a0 0x4>;
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+ clocks = <&osc24M>, <&pll6>;
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+ clock-output-names = "spi0";
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+ };
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+
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+ spi1_clk: clk@01c200a4 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a4 0x4>;
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+ clocks = <&osc24M>, <&pll6>;
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+ clock-output-names = "spi1";
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+ };
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+
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+ spi2_clk: clk@01c200a8 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a8 0x4>;
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+ clocks = <&osc24M>, <&pll6>;
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+ clock-output-names = "spi2";
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+ };
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+
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+ spi3_clk: clk@01c200ac {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200ac 0x4>;
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+ clocks = <&osc24M>, <&pll6>;
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+ clock-output-names = "spi3";
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+ };
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};
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soc@01c00000 {
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