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From: Gabor Juhos <juhosg@openwrt.org>
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Subject: debloat: add kernel config option to disabling common PCI quirks
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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drivers/pci/Kconfig | 6 ++++++
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drivers/pci/quirks.c | 6 ++++++
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2 files changed, 12 insertions(+)
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--- a/drivers/pci/Kconfig
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+++ b/drivers/pci/Kconfig
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@@ -71,6 +71,12 @@ config XEN_PCIDEV_FRONTEND
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The PCI device frontend driver allows the kernel to import arbitrary
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PCI devices from a PCI backend to support PCI driver domains.
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+config PCI_DISABLE_COMMON_QUIRKS
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+ bool "PCI disable common quirks"
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+ depends on PCI
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+ help
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+ If you don't know what to do here, say N.
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+
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config HT_IRQ
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bool "Interrupts on hypertransport devices"
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default y
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--- a/drivers/pci/quirks.c
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+++ b/drivers/pci/quirks.c
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@@ -41,6 +41,7 @@ static void quirk_mmio_always_on(struct
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
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+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
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/* The Mellanox Tavor device gives false positive parity errors
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* Mark this device with a broken_parity_status, to allow
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* PCI scanning code to "skip" this now blacklisted device.
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@@ -3038,6 +3039,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
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+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
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/*
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* Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
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@@ -3094,6 +3096,8 @@ static void fixup_debug_report(struct pc
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}
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}
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+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
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+
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/*
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* Some BIOS implementations leave the Intel GPU interrupts enabled,
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* even though no one is handling them (f.e. i915 driver is never loaded).
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@@ -3132,6 +3136,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
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+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
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+
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/*
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* PCI devices which are on Intel chips can skip the 10ms delay
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* before entering D3 mode.
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