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From efc0f99cebcab21dbabcc634b9dbb963bbbbcab8 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 27 Jul 2014 09:23:36 +0100
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Subject: [PATCH 07/57] MIPS: ralink: add support for MT7620n
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This is the small version of MT7620a.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/include/asm/mach-ralink/mt7620.h | 7 ++-----
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arch/mips/ralink/mt7620.c | 19 ++++++++++++-------
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2 files changed, 14 insertions(+), 12 deletions(-)
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--- a/arch/mips/include/asm/mach-ralink/mt7620.h
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+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
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@@ -25,11 +25,8 @@
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#define SYSC_REG_CPLL_CONFIG0 0x54
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#define SYSC_REG_CPLL_CONFIG1 0x58
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-#define MT7620N_CHIP_NAME0 0x33365452
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-#define MT7620N_CHIP_NAME1 0x20203235
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-
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-#define MT7620A_CHIP_NAME0 0x3637544d
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-#define MT7620A_CHIP_NAME1 0x20203032
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+#define MT7620_CHIP_NAME0 0x3637544d
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+#define MT7620_CHIP_NAME1 0x20203032
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#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -357,22 +357,27 @@ void prom_soc_init(struct ralink_soc_inf
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u32 cfg0;
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u32 pmu0;
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u32 pmu1;
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+ u32 bga;
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
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+ bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
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- if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
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- name = "MT7620N";
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- soc_info->compatible = "ralink,mt7620n-soc";
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- } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
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+ if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
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+ panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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+
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+ if (bga) {
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name = "MT7620A";
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soc_info->compatible = "ralink,mt7620a-soc";
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} else {
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- panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1);
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+ name = "MT7620N";
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+ soc_info->compatible = "ralink,mt7620n-soc";
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+#ifdef CONFIG_PCI
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+ panic("mt7620n is only supported for non pci kernels");
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+#endif
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}
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- rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
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-
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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"Ralink %s ver:%u eco:%u",
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name,
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