|
|
|
|
--- a/arch/mips/lantiq/irq.c
|
|
|
|
|
+++ b/arch/mips/lantiq/irq.c
|
|
|
|
|
@@ -67,7 +67,7 @@ int gic_present;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
static int exin_avail;
|
|
|
|
|
-static struct resource ltq_eiu_irq[MAX_EIU];
|
|
|
|
|
+static u32 ltq_eiu_irq[MAX_EIU];
|
|
|
|
|
static void __iomem *ltq_icu_membase[MAX_IM];
|
|
|
|
|
static void __iomem *ltq_eiu_membase;
|
|
|
|
|
static struct irq_domain *ltq_domain;
|
|
|
|
|
@@ -76,7 +76,7 @@ static int ltq_perfcount_irq;
|
|
|
|
|
int ltq_eiu_get_irq(int exin)
|
|
|
|
|
{
|
|
|
|
|
if (exin < exin_avail)
|
|
|
|
|
- return ltq_eiu_irq[exin].start;
|
|
|
|
|
+ return ltq_eiu_irq[exin];
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
@@ -128,7 +128,7 @@ static int ltq_eiu_settype(struct irq_da
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < MAX_EIU; i++) {
|
|
|
|
|
- if (d->hwirq == ltq_eiu_irq[i].start) {
|
|
|
|
|
+ if (d->hwirq == ltq_eiu_irq[i]) {
|
|
|
|
|
int val = 0;
|
|
|
|
|
int edge = 0;
|
|
|
|
|
|
|
|
|
|
@@ -176,7 +176,7 @@ static unsigned int ltq_startup_eiu_irq(
|
|
|
|
|
|
|
|
|
|
ltq_enable_irq(d);
|
|
|
|
|
for (i = 0; i < MAX_EIU; i++) {
|
|
|
|
|
- if (d->hwirq == ltq_eiu_irq[i].start) {
|
|
|
|
|
+ if (d->hwirq == ltq_eiu_irq[i]) {
|
|
|
|
|
/* by default we are low level triggered */
|
|
|
|
|
ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
|
|
|
|
|
/* clear all pending */
|
|
|
|
|
@@ -198,7 +198,7 @@ static void ltq_shutdown_eiu_irq(struct
|
|
|
|
|
|
|
|
|
|
ltq_disable_irq(d);
|
|
|
|
|
for (i = 0; i < MAX_EIU; i++) {
|
|
|
|
|
- if (d->hwirq == ltq_eiu_irq[i].start) {
|
|
|
|
|
+ if (d->hwirq == ltq_eiu_irq[i]) {
|
|
|
|
|
/* disable */
|
|
|
|
|
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
|
|
|
|
|
LTQ_EIU_EXIN_INEN);
|
|
|
|
|
@@ -343,10 +343,10 @@ static int icu_map(struct irq_domain *d,
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < exin_avail; i++)
|
|
|
|
|
- if (hw == ltq_eiu_irq[i].start)
|
|
|
|
|
+ if (hw == ltq_eiu_irq[i])
|
|
|
|
|
chip = <q_eiu_type;
|
|
|
|
|
|
|
|
|
|
- irq_set_chip_and_handler(hw, chip, handle_level_irq);
|
|
|
|
|
+ irq_set_chip_and_handler(irq, chip, handle_level_irq);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
@@ -441,14 +441,14 @@ int __init icu_of_init(struct device_nod
|
|
|
|
|
eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
|
|
|
|
|
if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
|
|
|
|
|
/* find out how many external irq sources we have */
|
|
|
|
|
- exin_avail = of_irq_count(eiu_node);
|
|
|
|
|
+ exin_avail = of_property_count_u32_elems(eiu_node, "lantiq,eiu-irqs");
|
|
|
|
|
|
|
|
|
|
if (exin_avail > MAX_EIU)
|
|
|
|
|
exin_avail = MAX_EIU;
|
|
|
|
|
|
|
|
|
|
- ret = of_irq_to_resource_table(eiu_node,
|
|
|
|
|
+ ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
|
|
|
|
|
ltq_eiu_irq, exin_avail);
|
|
|
|
|
- if (ret != exin_avail)
|
|
|
|
|
+ if (ret)
|
|
|
|
|
panic("failed to load external irq resources");
|
|
|
|
|
|
|
|
|
|
if (!request_mem_region(res.start, resource_size(&res),
|
