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89 lines
2.6 KiB
89 lines
2.6 KiB
9 years ago
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From 82f8582feef4c048ee7ef0155a71c23614a7856d Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Sat, 5 Dec 2015 21:16:44 +0800
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Subject: [PATCH] ARM: dts: sun4i: Add DRAM gates
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The DRAM gates controls direct memory access for some peripherals.
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These peripherals include the display pipeline, so add the required
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gates to the simplefb nodes as well.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun4i-a10.dtsi | 36 ++++++++++++++++++++++++++++++++----
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1 file changed, 32 insertions(+), 4 deletions(-)
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--- a/arch/arm/boot/dts/sun4i-a10.dtsi
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+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
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@@ -66,7 +66,7 @@
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-hdmi";
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clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
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- <&ahb_gates 44>;
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+ <&ahb_gates 44>, <&dram_gates 26>;
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status = "disabled";
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};
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@@ -75,7 +75,8 @@
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"simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
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clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
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- <&ahb_gates 44>, <&ahb_gates 46>;
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+ <&ahb_gates 44>, <&ahb_gates 46>,
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+ <&dram_gates 25>, <&dram_gates 26>;
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status = "disabled";
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};
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@@ -84,7 +85,8 @@
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"simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0";
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clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
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- <&ahb_gates 46>;
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+ <&ahb_gates 46>, <&dram_gates 25>,
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+ <&dram_gates 26>;
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status = "disabled";
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};
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@@ -93,7 +95,8 @@
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"simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
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clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
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- <&ahb_gates 44>, <&ahb_gates 46>;
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+ <&ahb_gates 44>, <&ahb_gates 46>,
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+ <&dram_gates 25>, <&dram_gates 26>;
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status = "disabled";
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};
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};
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@@ -492,6 +495,31 @@
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clock-output-names = "spi3";
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};
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+ dram_gates: clk@01c20100 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-a10-dram-gates-clk";
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+ reg = <0x01c20100 0x4>;
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+ clocks = <&pll5 0>;
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+ clock-indices = <0>,
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+ <1>, <2>,
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+ <3>,
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+ <4>,
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+ <5>, <6>,
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+ <15>,
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+ <24>, <25>,
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+ <26>, <27>,
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+ <28>, <29>;
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+ clock-output-names = "dram_ve",
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+ "dram_csi0", "dram_csi1",
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+ "dram_ts",
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+ "dram_tvd",
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+ "dram_tve0", "dram_tve1",
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+ "dram_output",
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+ "dram_de_fe1", "dram_de_fe0",
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+ "dram_de_be0", "dram_de_be1",
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+ "dram_de_mp", "dram_ace";
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+ };
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+
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codec_clk: clk@01c20140 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-codec-clk";
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