--- a/arch/mips/pci/pci-mt7620.c
+++ b/arch/mips/pci/pci-mt7620.c
@@ -35,6 +35,7 @@
 #define PPLL_CFG1			0x9c
 
 #define PPLL_DRV			0xa0
+#define PPLL_LD			(1<<23)
 #define PDRV_SW_SET			(1<<31)
 #define LC_CKDRVPD			(1<<19)
 #define LC_CKDRVOHZ			(1<<18)
@@ -242,8 +243,8 @@ static int mt7620_pci_hw_init(struct pla
 	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 	mdelay(100);
 
-	if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
-		dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
+	if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
+		dev_err(&pdev->dev, "MT7620 PPLL is unlocked, aborting init\n");
 		reset_control_assert(rstpcie0);
 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 		return -1;
